fpga: switched to xilinx.mk and removed non essential overrides

Bender.lock

@@ -233,7 +233,7 @@ packages:
     dependencies:
     - common_cells
   fpu_interco:
-    revision: 0769976fa51bdd820656a01161a4c46b88c59ac5
+    revision: c985d54c2b078ddfbec8c2a498f453410bbdc93e
     version: null
     source:
       Git: https://github.com/pulp-platform/fpu_interco.git
@@ -371,7 +371,7 @@ packages:
     dependencies:
     - axi_slice
   pulp_cluster:
-    revision: a746000f9dc9965e1351186905b59bca36edef57
+    revision: 314f9a04f8dad4a5eeb0b9e8ad84898c6dc3f81e
     version: null
     source:
       Git: https://github.com/pulp-platform/pulp_cluster.git
@@ -433,7 +433,7 @@ packages:
     - common_cells
     - common_verification
   riscv:
-    revision: 4eac53237c6d0062715d17016fe95462eb81ebc3
+    revision: 6187537f9994d16bad2d721c0f5ebc5193c0f010
     version: null
     source:
       Git: [email protected]:AlSaqr-platform/riscv_nn.git

Bender.yml

@@ -16,7 +16,7 @@ dependencies:
   hyperbus:           { git: https://github.com/pulp-platform/hyperbus.git,             rev: 2adb7271438cdb96c19fbaf3e2a6bf89ffeee568 } # branch: lv/phys_in_use
   car_l2:             { git: [email protected]:carfield/carfield_l2_mem.git,       rev: 08503a05307ef556ed5439619c70c039ff93d77a } # branch: main
   safety_island:      { git: [email protected]:carfield/safety-island.git,         rev: 60e768a3ef29f47339e31674d497293f5a768893 } # branch: atops
-  pulp_cluster:       { git: https://github.com/pulp-platform/pulp_cluster.git,         rev: a746000f9dc9965e1351186905b59bca36edef57 } # branch: yt/carfield-integration
+  pulp_cluster:       { git: https://github.com/pulp-platform/pulp_cluster.git,         rev: 314f9a04f8dad4a5eeb0b9e8ad84898c6dc3f81e } # branch: yt/carfield-integration
   opentitan:          { git: https://github.com/alsaqr-platform/opentitan.git,          rev: cce5a6e0bacba31374109969adcd7abb0f70f7ec } # branch: yt/hartid
   mailbox_unit:       { git: [email protected]:pulp-platform/mailbox_unit.git,             version: 1.1.0                                }
   apb:                { git: https://github.com/pulp-platform/apb.git,                  version: 0.2.3                                }
@@ -69,11 +69,7 @@ sources:
       - target/xilinx/src/carfield_top_xilinx.sv
       - target/xilinx/src/dram_wrapper.sv
       # Override certain files due to vivado related errors
-      - target/xilinx/src/overrides/cv32e40p_fpu_wrap.sv
-      - target/xilinx/src/overrides/fpnew_wrapper.sv
       - target/xilinx/src/overrides/tc_clk_xilinx.sv
-      - target/xilinx/src/overrides/tc_sram_xilinx.sv
-      - target/xilinx/src/overrides/riscv_ex_stage.sv
 
 vendor_package:
   - name: reggen

bender-xilinx.mk

@@ -0,0 +1,25 @@
+# Copyright 2021 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Author: Cyril Koenig <[email protected]>
+
+# bender targets
+xilinx_targs += -t fpga
+
+# bender defines
+xilinx_defs += -D PULP_FPGA_EMUL
+
+# Conditionally add GEN_{island} to bender define
+define check_enable_island
+ifeq ($($(1)),1)
+xilinx_defs += $(1)
+endif
+endef
+
+$(eval $(call check_enable_island,GEN_PULP_CLUSTER))
+$(eval $(call check_enable_island,GEN_SAFETY_ISLAND))
+$(eval $(call check_enable_island,GEN_SPATZ_CLUSTER))
+$(eval $(call check_enable_island,GEN_OPEN_TITAN))
+
+# note : bender targets are later modified in xilinx.mk

carfield.mk

@@ -9,10 +9,12 @@
 CAR_ROOT ?= .
 CHS_ROOT ?= $(CAR_ROOT)/cheshire
 CAR_SW_DIR := $(CAR_ROOT)/sw
+CAR_XIL_DIR := $(CAR_ROOT)/target/xilinx
 
 # Bender
 BENDER   ?= bender
 QUESTA   ?= questa-2022.3
+VIVADO   ?= vitis-2020.2 vivado
 TBENCH   ?= tb_carfield_soc
 BOOTMODE ?= 0 # default passive bootmode
 PRELMODE ?= 1 # default serial link preload
@@ -43,6 +45,10 @@ CHS_IMAGE    ?=
 # (the following includes are mandatory)
 include $(CAR_ROOT)/bender-common.mk
 include $(CAR_ROOT)/bender-synth.mk
+include $(CAR_ROOT)/bender-xilinx.mk
+
+print_stuff:
+	echo $(xilinx_defs)
 
 # Setup Virtual Environment for python scripts (reggen)
 VENVDIR?=$(WORKDIR)/.venv
@@ -235,6 +241,16 @@ SPYGLASS_DEFS += $(synth_defs)
 lint:
 	$(MAKE) -C scripts lint bender_defs="$(SPYGLASS_DEFS)" bender_targs="$(SPYGLASS_TARGS)" > make.log
 
+#############
+# Emulation #
+#############
+
+include $(CAR_XIL_DIR)/xilinx.mk
+
+########
+# Help #
+########
+
 # Setup Autodocumentation of the Makefile
 HELP_TITLE="Carfield Open-Source RTL"
 HELP_DESCRIPTION="Hardware generation and simulation targets for Carfield"