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banshee: Add runtime for unit tests (#18)
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* banshee: Add runtime for unit tests

Add a dedicated runtime library for banshee's unit tests. This allows
the simulator to remain largely independent from any other software
development efforts around a runtime, and keeps the tests minimal and
self-contained.

* banshee: Fix license headers

* banshee: Fix python formatting

* banshee: clang-format
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fabianschuiki authored Jan 25, 2021
1 parent 14a3dc1 commit de73ace
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Showing 44 changed files with 3,088 additions and 979 deletions.
2 changes: 2 additions & 0 deletions .clang-format-ignore
Original file line number Diff line number Diff line change
Expand Up @@ -7,5 +7,7 @@
./sw/vendor/*
./sw/banshee/vendor/*
./sw/banshee/build/*
./sw/banshee/tests/runtime/printf.*
./sw/banshee/tests/runtime/encoding.h
# Ignore any checked-out directories
*/.bender/*
8 changes: 3 additions & 5 deletions sw/banshee/tests/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -2,9 +2,7 @@
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

DIR := $(shell dirname $(abspath $(lastword $(MAKEFILE_LIST))))/../../sw
VPATH += $(DIR)
include $(DIR)/runtime/runtime.mk
include runtime/runtime.mk

all: bin/large_lfsr
all: bin/dummy
Expand All @@ -25,13 +23,13 @@ all: bin/far_jump

bin/%: %.c
mkdir -p $(shell dirname $@) dump
$(RISCV_CC) -Iinclude $(RISCV_LDFLAGS) -o $@ $^ -T$(DIR)/runtime/link.ld $(DIR)/runtime/billywig_crt0.S
$(RISCV_CC) -Iinclude $(RISCV_LDFLAGS) -o $@ $^ -Truntime/link.ld runtime/billywig_crt0.S
$(RISCV_STRIP) $@ -g -S -d --strip-debug
$(RISCV_OBJDUMP) -D $@ > dump/$*.dump

bin/%: %.s
mkdir -p $(shell dirname $@) dump
$(RISCV_CC) -Iinclude $(RISCV_LDFLAGS) -o $@ $^ -T$(DIR)/runtime/link.ld
$(RISCV_CC) -Iinclude $(RISCV_LDFLAGS) -o $@ $^ -Truntime/link.ld
$(RISCV_STRIP) $@ -g -S -d --strip-debug
$(RISCV_OBJDUMP) -D $@ > dump/$*.dump

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107 changes: 56 additions & 51 deletions sw/banshee/tests/dump/frep_multiple.dump
Original file line number Diff line number Diff line change
Expand Up @@ -20,54 +20,57 @@ Disassembly of section .text:
80010010: ffc10113 addi sp,sp,-4 # 40000008 <tcdm_end_address_reg>
80010014: 00012103 lw sp,0(sp)
80010018: f1402573 csrr a0,mhartid
8001001c: 00351293 slli t0,a0,0x3
80010020: 40510133 sub sp,sp,t0
80010024: 00629293 slli t0,t0,0x6
80010028: 40510133 sub sp,sp,t0
8001002c: 00010213 mv tp,sp
80010030: 00100293 li t0,1
80010034: 00929293 slli t0,t0,0x9
80010038: 40520233 sub tp,tp,t0
8001003c: bfff0297 auipc t0,0xbfff0
80010040: fd428293 addi t0,t0,-44 # 40000010 <nr_cores_address_reg>
80010044: 0002a583 lw a1,0(t0)
80010048: 038000ef jal ra,80010080 <main>
8001004c: 00151513 slli a0,a0,0x1
80010050: 00156513 ori a0,a0,1
80010054: 0100006f j 80010064 <eoc>

80010058 <fail>:
80010058: fff00293 li t0,-1
8001005c: 00554533 xor a0,a0,t0
80010060: 0040006f j 80010064 <eoc>

80010064 <eoc>:
80010064: f14022f3 csrr t0,mhartid
80010068: 00029863 bnez t0,80010078 <halt>
8001006c: bfff0297 auipc t0,0xbfff0
80010070: fb428293 addi t0,t0,-76 # 40000020 <scratch_reg>
80010074: 00a2a023 sw a0,0(t0)

80010078 <halt>:
80010078: 10500073 wfi
8001007c: ffdff06f j 80010078 <halt>
8001001c: bfff0297 auipc t0,0xbfff0
80010020: 0242a283 lw t0,36(t0) # 40000040 <cluster_base_hart_id_reg>
80010024: 40550533 sub a0,a0,t0
80010028: 00351293 slli t0,a0,0x3
8001002c: 40510133 sub sp,sp,t0
80010030: 00629293 slli t0,t0,0x6
80010034: 40510133 sub sp,sp,t0
80010038: 00010213 mv tp,sp
8001003c: 00100293 li t0,1
80010040: 00929293 slli t0,t0,0x9
80010044: 40520233 sub tp,tp,t0
80010048: bfff0297 auipc t0,0xbfff0
8001004c: fc828293 addi t0,t0,-56 # 40000010 <nr_cores_address_reg>
80010050: 0002a583 lw a1,0(t0)
80010054: 038000ef jal ra,8001008c <main>
80010058: 00151513 slli a0,a0,0x1
8001005c: 00156513 ori a0,a0,1
80010060: 0100006f j 80010070 <eoc>

80010064 <fail>:
80010064: fff00293 li t0,-1
80010068: 00554533 xor a0,a0,t0
8001006c: 0040006f j 80010070 <eoc>

80010070 <eoc>:
80010070: f14022f3 csrr t0,mhartid
80010074: 00029863 bnez t0,80010084 <halt>
80010078: bfff0297 auipc t0,0xbfff0
8001007c: fa828293 addi t0,t0,-88 # 40000020 <scratch_reg>
80010080: 00a2a023 sw a0,0(t0)

80010084 <halt>:
80010084: 10500073 wfi
80010088: ffdff06f j 80010084 <halt>

Disassembly of section .text.startup:

80010080 <main>:
80010080: 00000797 auipc a5,0x0
80010084: 0407b707 fld fa4,64(a5) # 800100c0 <main+0x40>
80010088: 00000797 auipc a5,0x0
8001008c: 0407b687 fld fa3,64(a5) # 800100c8 <main+0x48>
80010090: d20007d3 fcvt.d.w fa5,zero
80010094: 0012808b 0x12808b
80010098: 02e7f7d3 fadd.d fa5,fa5,fa4
8001009c: 12d7f7d3 fmul.d fa5,fa5,fa3
800100a0: 00000797 auipc a5,0x0
800100a4: 0307b707 fld fa4,48(a5) # 800100d0 <main+0x50>
800100a8: a2e7a553 feq.d a0,fa5,fa4
800100ac: 00154513 xori a0,a0,1
800100b0: 00008067 ret
8001008c <main>:
8001008c: 00000797 auipc a5,0x0
80010090: 0347b707 fld fa4,52(a5) # 800100c0 <main+0x34>
80010094: 00000797 auipc a5,0x0
80010098: 0347b687 fld fa3,52(a5) # 800100c8 <main+0x3c>
8001009c: d20007d3 fcvt.d.w fa5,zero
800100a0: 0012808b 0x12808b
800100a4: 02e7f7d3 fadd.d fa5,fa5,fa4
800100a8: 12d7f7d3 fmul.d fa5,fa5,fa3
800100ac: 00000797 auipc a5,0x0
800100b0: 0247b707 fld fa4,36(a5) # 800100d0 <main+0x44>
800100b4: a2e7a553 feq.d a0,fa5,fa4
800100b8: 00154513 xori a0,a0,1
800100bc: 00008067 ret

Disassembly of section .sdata:

Expand All @@ -91,20 +94,20 @@ Disassembly of section .comment:
0: 3a434347 fmsub.d ft6,ft6,ft4,ft7,rmm
4: 2820 fld fs0,80(s0)
6: 29554e47 fmsub.s ft8,fa0,fs5,ft5,rmm
a: 3920 fld fs0,112(a0)
c: 322e fld ft4,232(sp)
e: 302e fld ft0,232(sp)
...
a: 3120 fld fs0,96(a0)
c: 2e30 fld fa2,88(a2)
e: 2e32 fld ft8,264(sp)
10: 0030 addi a2,sp,8

Disassembly of section .riscv.attributes:

00000000 <.riscv.attributes>:
0: 2f41 jal 790 <l1_alloc_base+0x780>
0: 3341 jal fffffd80 <fake_uart+0x3ffffd80>
2: 0000 unimp
4: 7200 flw fs0,32(a2)
6: 7369 lui t1,0xffffa
8: 01007663 bgeu zero,a6,14 <l1_alloc_base+0x4>
c: 0025 c.nop 9
c: 0029 c.nop 10
e: 0000 unimp
10: 1004 addi s1,sp,32
12: 7205 lui tp,0xfffe1
Expand All @@ -118,3 +121,5 @@ Disassembly of section .riscv.attributes:
26: 3266 fld ft4,120(sp)
28: 3070 fld fa2,224(s0)
2a: 645f 7032 0030 0x307032645f
30: 0108 addi a0,sp,128
32: 0b0a slli s6,s6,0x2
109 changes: 57 additions & 52 deletions sw/banshee/tests/dump/frep_single.dump
Original file line number Diff line number Diff line change
Expand Up @@ -12,68 +12,71 @@ Disassembly of section .text:

80010000 <_start>:
80010000: 00001197 auipc gp,0x1
80010004: 8b018193 addi gp,gp,-1872 # 800108b0 <__global_pointer$>
80010004: 8c018193 addi gp,gp,-1856 # 800108c0 <__global_pointer$>
80010008: 0040006f j 8001000c <reset_vector>

8001000c <reset_vector>:
8001000c: bfff0117 auipc sp,0xbfff0
80010010: ffc10113 addi sp,sp,-4 # 40000008 <tcdm_end_address_reg>
80010014: 00012103 lw sp,0(sp)
80010018: f1402573 csrr a0,mhartid
8001001c: 00351293 slli t0,a0,0x3
80010020: 40510133 sub sp,sp,t0
80010024: 00629293 slli t0,t0,0x6
80010028: 40510133 sub sp,sp,t0
8001002c: 00010213 mv tp,sp
80010030: 00100293 li t0,1
80010034: 00929293 slli t0,t0,0x9
80010038: 40520233 sub tp,tp,t0
8001003c: bfff0297 auipc t0,0xbfff0
80010040: fd428293 addi t0,t0,-44 # 40000010 <nr_cores_address_reg>
80010044: 0002a583 lw a1,0(t0)
80010048: 038000ef jal ra,80010080 <main>
8001004c: 00151513 slli a0,a0,0x1
80010050: 00156513 ori a0,a0,1
80010054: 0100006f j 80010064 <eoc>

80010058 <fail>:
80010058: fff00293 li t0,-1
8001005c: 00554533 xor a0,a0,t0
80010060: 0040006f j 80010064 <eoc>

80010064 <eoc>:
80010064: f14022f3 csrr t0,mhartid
80010068: 00029863 bnez t0,80010078 <halt>
8001006c: bfff0297 auipc t0,0xbfff0
80010070: fb428293 addi t0,t0,-76 # 40000020 <scratch_reg>
80010074: 00a2a023 sw a0,0(t0)

80010078 <halt>:
80010078: 10500073 wfi
8001007c: ffdff06f j 80010078 <halt>
8001001c: bfff0297 auipc t0,0xbfff0
80010020: 0242a283 lw t0,36(t0) # 40000040 <cluster_base_hart_id_reg>
80010024: 40550533 sub a0,a0,t0
80010028: 00351293 slli t0,a0,0x3
8001002c: 40510133 sub sp,sp,t0
80010030: 00629293 slli t0,t0,0x6
80010034: 40510133 sub sp,sp,t0
80010038: 00010213 mv tp,sp
8001003c: 00100293 li t0,1
80010040: 00929293 slli t0,t0,0x9
80010044: 40520233 sub tp,tp,t0
80010048: bfff0297 auipc t0,0xbfff0
8001004c: fc828293 addi t0,t0,-56 # 40000010 <nr_cores_address_reg>
80010050: 0002a583 lw a1,0(t0)
80010054: 038000ef jal ra,8001008c <main>
80010058: 00151513 slli a0,a0,0x1
8001005c: 00156513 ori a0,a0,1
80010060: 0100006f j 80010070 <eoc>

80010064 <fail>:
80010064: fff00293 li t0,-1
80010068: 00554533 xor a0,a0,t0
8001006c: 0040006f j 80010070 <eoc>

80010070 <eoc>:
80010070: f14022f3 csrr t0,mhartid
80010074: 00029863 bnez t0,80010084 <halt>
80010078: bfff0297 auipc t0,0xbfff0
8001007c: fa828293 addi t0,t0,-88 # 40000020 <scratch_reg>
80010080: 00a2a023 sw a0,0(t0)

80010084 <halt>:
80010084: 10500073 wfi
80010088: ffdff06f j 80010084 <halt>

Disassembly of section .text.startup:

80010080 <main>:
80010080: 00400293 li t0,4
80010084: 00000797 auipc a5,0x0
80010088: 02c7b707 fld fa4,44(a5) # 800100b0 <main+0x30>
8001008c: d20007d3 fcvt.d.w fa5,zero
80010090: 0002808b 0x2808b
80010094: 02e7f7d3 fadd.d fa5,fa5,fa4
80010098: 00500793 li a5,5
8001009c: d2078753 fcvt.d.w fa4,a5
800100a0: a2f72553 feq.d a0,fa4,fa5
800100a4: 00154513 xori a0,a0,1
800100a8: 00008067 ret
8001008c <main>:
8001008c: 00400293 li t0,4
80010090: 00000797 auipc a5,0x0
80010094: 0307b707 fld fa4,48(a5) # 800100c0 <main+0x34>
80010098: d20007d3 fcvt.d.w fa5,zero
8001009c: 0002808b 0x2808b
800100a0: 02e7f7d3 fadd.d fa5,fa5,fa4
800100a4: 00500793 li a5,5
800100a8: d2078753 fcvt.d.w fa4,a5
800100ac: a2f72553 feq.d a0,fa4,fa5
800100b0: 00154513 xori a0,a0,1
800100b4: 00008067 ret

Disassembly of section .sdata:

800100b0 <__bss_end-0x8>:
800100b0: 0000 unimp
800100b2: 0000 unimp
800100b4: 0000 unimp
800100b6: 3ff0 fld fa2,248(a5)
800100c0 <__bss_end-0x8>:
800100c0: 0000 unimp
800100c2: 0000 unimp
800100c4: 0000 unimp
800100c6: 3ff0 fld fa2,248(a5)

Disassembly of section .comment:

Expand All @@ -83,18 +86,18 @@ Disassembly of section .comment:
6: 29554e47 fmsub.s ft8,fa0,fs5,ft5,rmm
a: 3120 fld fs0,96(a0)
c: 2e30 fld fa2,88(a2)
e: 2e31 jal 32a <l1_alloc_base+0x31a>
e: 2e32 fld ft8,264(sp)
10: 0030 addi a2,sp,8

Disassembly of section .riscv.attributes:

00000000 <.riscv.attributes>:
0: 2f41 jal 790 <l1_alloc_base+0x780>
0: 3341 jal fffffd80 <fake_uart+0x3ffffd80>
2: 0000 unimp
4: 7200 flw fs0,32(a2)
6: 7369 lui t1,0xffffa
8: 01007663 bgeu zero,a6,14 <l1_alloc_base+0x4>
c: 0025 c.nop 9
c: 0029 c.nop 10
e: 0000 unimp
10: 1004 addi s1,sp,32
12: 7205 lui tp,0xfffe1
Expand All @@ -108,3 +111,5 @@ Disassembly of section .riscv.attributes:
26: 3266 fld ft4,120(sp)
28: 3070 fld fa2,224(s0)
2a: 645f 7032 0030 0x307032645f
30: 0108 addi a0,sp,128
32: 0b0a slli s6,s6,0x2
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