script: Use include_str! for templates

src/script_fmt/flist.tera

@@ -0,0 +1,21 @@
+{% for incdir in all_incdirs %}{#                                             loop over all include directories
+#}{% if relativize_path %}{#                                                  make path relative if necessary
+#}+incdir+{{ incdir | replace(from=root, to='') }}
+{% else %}{#
+#}+incdir+{{ incdir }}
+{% endif %}{#
+#}{% endfor %}{#
+#}{% for define in all_defines %}{#                                           loop over all defines
+#}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}
+{% endfor %}{#
+#}{% for file in all_files %}{#                                               loop over all files
+#}{% if relativize_path %}{#                                                  make path relative if necessary
+#}{% if file is starting_with(root) %}{#                                      keep path unless it starts with common root
+#}{{ file | replace(from=root, to='') | trim_start_matches(pat='/') }}
+{% else %}{#
+#}{{ file }}
+{% endif %}{#
+#}{% else %}{#
+#}{{ file }}
+{% endif %}{#
+#}{% endfor %}

src/script_fmt/formality_tcl.tera

@@ -0,0 +1,37 @@
+# {{HEADER_AUTOGEN}}
+set ROOT "{{ root }}"
+set search_path_initial $search_path
+{% if compilation_mode == 'separate' %}{% for group in srcs %}
+set search_path $search_path_initial
+{% for incdir in group.incdirs %}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}"
+{% endfor %}
+{% if abort_on_error %}if {[catch { {% endif %}{% if group.file_type == 'verilog' %}read_sverilog{% elif group.file_type == 'vhdl' %}read_vhdl{% endif %} -r \
+    {% for define in group.defines %}{% if loop.first %}-define { \
+        {% endif %}{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
+    } \
+    {% else %} \
+        {% endif %}{% endfor %}[list \
+    {% for file in group.files %}{{ '    ' }}"{{ file | replace(from=root, to='$ROOT') }}" \
+    {% endfor %}]
+{% if abort_on_error %}}]} {return 1}{% endif %}
+{% endfor %}
+{% else %}{# compilation_mode == 'common' #}{% for file in all_verilog %}{% if loop.first %}set search_path $search_path_initial
+{% for incdir in all_incdirs %}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}"
+{% endfor %}
+{% if abort_on_error %}if {[catch { {% endif %}read_sverilog -r \
+    {% for define in all_defines %}{% if loop.first %}-define { \
+        {% endif %}{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
+    } \
+    {% else %} \
+        {% endif %}{% endfor %}[list \
+    {% endif %}{{ '    ' }}"{{ file | replace(from=root, to='$ROOT') }}" \
+    {% if loop.last %}]
+{% if abort_on_error %}}]} {return 1}{% endif %}
+{% endif %}{% endfor %}
+{% for file in all_vhdl %}{% if loop.first %}{% if abort_on_error %}if {[catch { {% endif %}read_vhdl -r \
+    [list \
+    {% endif %}{{ '    ' }}"{{ file | replace(from=root, to='$ROOT') }}" \
+    {% if loop.last %}]
+{% if abort_on_error %}}]} {return 1}{% endif %}
+{% endif %}{% endfor %}
+{% endif %}set search_path $search_path_initial

src/script_fmt/genus_tcl.tera

@@ -0,0 +1,43 @@
+# {{ HEADER_AUTOGEN }}
+if [ info exists search_path ] {{ '{{' }}
+  set search_path_initial $search_path
+{{ '}}' }}
+set ROOT = "{{ root }}"
+{% if compilation_mode == 'separate' %}{% for group in srcs %}
+set search_path $search_path_initial
+{% for incdir in group.incdirs %}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}"
+{% endfor %}set_db init_hdl_search_path $search_path
+
+{% if group.file_type == 'verilog' %}read_hdl -language sv \
+    {% elif group.file_type == 'vhdl' %}read_hdl -language vhdl \
+    {% endif %}{% for define in group.defines %}{% if loop.first %}-define { \
+        {% endif %}{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
+    } \
+    {% else %} \
+        {% endif %}{% endfor %}[list \
+    {% for file in group.files %}{{ '    ' }}"{{ file | replace(from=root, to='$ROOT') }}" \
+    {% endfor %}]
+{% endfor %}
+{% else %}{# compilation_mode == 'common' #}{% for file in all_verilog %}{% if loop.first %}set search_path $search_path_initial
+{% for incdir in all_incdirs %}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}"
+{% endfor %}
+set_db init_hdl_search_path $search_path
+
+{% if abort_on_error %}if {[catch { {% endif %}read_hdl -language sv \
+    {% for define in all_defines %}{% if loop.first %}-define { \
+        {% endif %}{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
+    } \
+    {% else %} \
+        {% endif %}{% endfor %}[list \
+    {% endif %}{{ '    ' }}"{{ file | replace(from=root, to='$ROOT') }}" \
+    {% if loop.last %}]
+{% if abort_on_error %}}]} {return 1}{% endif %}
+{% endif %}{% endfor %}
+{% for file in all_vhdl %}{% if loop.first %}
+{% if abort_on_error %}if {[catch { {% endif %}read_hdl -language vhdl \
+    [list \
+    {% endif %}{{ '    ' }}"{{ file | replace(from=root, to='$ROOT') }}" \
+    {% if loop.last %}]
+{% if abort_on_error %}}]} {return 1}{% endif %}
+{% endif %}{% endfor %}
+{% endif %}set search_path $search_path_initial

src/script_fmt/precision_tcl.tera

@@ -0,0 +1,49 @@
+# {{ HEADER_AUTOGEN }}
+# Precision does not take relative paths into account when specifying include dirs.
+# Define the common ROOT anyway if needed for patching file paths.
+set ROOT {{ root }}
+set_input_dir $ROOT
+setup_design -search_path $ROOT
+{% for define in all_defines %}{% if loop.first %}
+# Set globally all defines for the (S)Verilog sources.
+setup_design -defines { \
+    {% endif %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %}
+
+{% else %} \
+    {% endif %}{% endfor %}{% if compilation_mode == 'separate' %}{% for group in srcs %}{% if abort_on_error %}if {[catch { {% endif %}add_input_file \
+    {% if group.file_type == 'verilog' %}-format SystemVerilog2012 \
+    {% for incdir in group.incdirs %}{% if loop.first %}-search_path { \
+        {% endif %}{{ incdir }}{% if loop.last %} \
+    } \
+    {% else %} \
+        {% endif %}{% endfor %}{% elif group.file_type == 'vhdl' %}-format vhdl_2008 \
+    {% endif %}{ \
+        {% for file in group.files %}{{ file }}{% if loop.last %} \
+    {% else %} \
+        {% endif %}{% endfor %}} \
+{% if abort_on_error %}}]} {return 1}
+{% endif %}
+{% endfor %}
+{% else %}{# compilation_mode == 'common' #}{% for file in all_verilog %}{% if loop.first %}{% if abort_on_error %}if {[catch { {% endif %}add_input_file \
+    -format SystemVerilog2012 \
+    {% for incdir in all_incdirs %}{% if loop.first %}-search_path { \
+        {% endif %}{{ incdir }}{% if loop.last %} \
+    } \
+    {% else %} \
+        {% endif %}{% endfor %}{ \
+        {% endif %}{{ file }}{% if loop.last %} \
+    {% else %} \
+        {% endif %}{% if loop.last %}} \
+{% if abort_on_error %}}]} {return 1}
+{% endif %}
+{% endif %}{% endfor %}
+{% for file in all_vhdl %}{% if loop.first %}{% if abort_on_error %}if {[catch { {% endif %}add_input_file \
+    -format vhdl_2008 \
+    { \
+        {% endif %}{{ file }}{% if loop.last %} \
+    {% else %} \
+        {% endif %}{% if loop.last %}} \
+{% if abort_on_error %}}]} {return 1}
+{% endif %}
+{% endif %}{% endfor %}
+{% endif %}

src/script_fmt/riviera_tcl.tera

@@ -0,0 +1,28 @@
+# {{ HEADER_AUTOGEN }}
+set ROOT "{{ root }}"
+vlib work
+{% if compilation_mode == 'separate' %}{% for group in srcs %}{% if abort_on_error %}if {[catch { {% endif %}{% if group.file_type == 'verilog' %}vlog -sv \
+    {% for tmp_arg in vlog_args %}{{ tmp_arg }} \
+    {% endfor %}{% for define in group.defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \
+    {% endfor %}{% for incdir in group.incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
+    {% endfor %}{% elif group.file_type == 'vhdl' %}vcom -2008 \
+    {% for tmp_arg in vcom_args %}{{ tmp_arg }} \
+    {% endfor %}{% endif %}{% for file in group.files %}"{{ file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
+    {% else %}\
+{% endif %}{% endfor %}{% if abort_on_error %}}]} {return 1}{% endif %}
+
+{% endfor %}{% else %}{# compilation_mode == 'common' #}{% for file in all_verilog %}{% if loop.first %}{% if abort_on_error %}if {[catch { {% endif %}vlog -sv \
+    {% for tmp_arg in vlog_args %}{{ tmp_arg }} \
+    {% endfor %}{% for define in all_defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \
+    {% endfor %}{% for incdir in all_incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
+    {% endfor %}{% endif %}"{{ file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
+    {% else %}\
+{% endif %}{% if loop.last %}{% if abort_on_error %}}]} {return 1}{% endif %}
+
+{% endif %}{% endfor %}{% for file in all_vhdl %}{% if loop.first %}{% if abort_on_error %}if {[catch { {% endif %}vcom -2008 \
+    {% for tmp_arg in vcom_args %}{{ tmp_arg }} \
+    {% endfor %}{% endif %}"{{ file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
+    {% else %}\
+{% endif %}{% if loop.last %}{% if abort_on_error %}}]} {return 1}{% endif %}
+
+{% endif %}{% endfor %}{% endif %}

src/script_fmt/synopsys_tcl.tera

@@ -0,0 +1,50 @@
+# {{HEADER_AUTOGEN}}
+set ROOT "{{ root }}"
+set search_path_initial $search_path
+{% if compilation_mode == 'separate' %}{#                                                                           Individual block for each source file group
+#}{% for group in srcs %}
+set search_path $search_path_initial
+{% for incdir in group.incdirs %}{#                                                                                 Add group's include directories
+#}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}"
+{% endfor %}
+{% if abort_on_error %}if {[catch { {% endif %}{#                                                                      Catch errors immediately
+#}analyze -format {% if group.file_type == 'verilog' %}sv{% elif group.file_type == 'vhdl' %}vhdl{% endif %} \{#    Analyze command for SystemVerilog or VHDL #}
+    {% for define in group.defines %}{#                                                                             Add group's defines
+#}{% if loop.first %}-define { \
+        {% endif %}{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
+    } \
+    {% else %} \
+        {% endif %}{% endfor %}[list \
+    {% for file in group.files %}{#                                                                                 Add group's files
+#}{{ '    ' }}"{{ file | replace(from=root, to='$ROOT') }}" \
+    {% endfor %}]
+{% if abort_on_error %}}]} {return 1}{% endif %}
+{% endfor %}
+{% else %}{# compilation_mode == 'common' #}{#                                                                      Common block for all files
+#}{% for file in all_verilog %}{#                                                                                   Loop over verilog files
+#}{% if loop.first %}set search_path $search_path_initial
+{% for incdir in all_incdirs %}{#                                                                                   Add all include directories
+#}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}"
+{% endfor %}
+{% if abort_on_error %}if {[catch { {% endif %}{#                                                                      Catch errors immediately
+#}analyze -format sv \{#                                                                                            Analyze command for SystemVerilog #}
+    {% for define in all_defines %}{#                                                                               Add all defines
+}
+#}{% if loop.first %}-define { \
+        {% endif %}{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
+    } \
+    {% else %} \
+        {% endif %}{% endfor %}[list \
+    {% endif %}{{ '    ' }}"{{ file | replace(from=root, to='$ROOT') }}" \{#                                        Add all verilog files #}
+    {% if loop.last %}]
+{% if abort_on_error %}}]} {return 1}{% endif %}
+{% endif %}{% endfor %}
+{% for file in all_vhdl %}{% if loop.first %}{#                                                                     Loop over all VHDL files
+#}{% if abort_on_error %}if {[catch { {% endif %}{#                                                                    Catch errors immediately
+#}analyze -format vhdl \{#                                                                                          Analyze command for VHDL #}
+    [list \
+    {% endif %}{{ '    ' }}"{{ file | replace(from=root, to='$ROOT') }}" \{#                                        Add all VHDL files #}
+    {% if loop.last %}]
+{% if abort_on_error %}}]} {return 1}{% endif %}
+{% endif %}{% endfor %}
+{% endif %}set search_path $search_path_initial

src/script_fmt/vcs_sh.tera

@@ -0,0 +1,28 @@
+#!/usr/bin/env bash
+# {{ HEADER_AUTOGEN }}
+ROOT="{{ root }}"
+{% if compilation_mode == 'separate' %}{% for group in srcs %}
+{% if group.file_type == 'verilog' %}{{ vlogan_bin }} -sverilog \
+    -full64 \
+    {% for tmp_arg in vlog_args %}{{ tmp_arg }} \
+    {% endfor %}{% for define in group.defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \
+    {% endfor %}{% for incdir in group.incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
+    {% endfor %}{% elif group.file_type == 'vhdl' %}{{ vhdlan_bin }} \
+    {% for tmp_arg in vcom_args %}{{ tmp_arg }} \
+    {% endfor %}{% endif %}{% for file in group.files %}"{{ file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
+    {% endif %}{% endfor %}
+{% endfor %}
+{% else %}{# compilation_mode == 'common' #}{% for file in all_verilog %}{% if loop.first %}{{ vlogan_bin }} -sverilog \
+    -full64 \
+    {% for tmp_arg in vlog_args %}{{ tmp_arg }} \
+    {% endfor %}{% for define in all_defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \
+    {% endfor %}{% for incdir in all_incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
+    {% endfor %}{% endif %}"{{ file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
+    {% endif %}{% if loop.last %}
+{% endif %}{% endfor %}
+{% for file in all_vhdl %}{% if loop.first %}{{ vhdlan_bin }} \
+    {% for tmp_arg in vcom_args %}{{ tmp_arg }} \
+    {% endfor %}{% endif %}"{{ file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
+    {% endif %}{% if loop.last %}
+{% endif %}{% endfor %}
+{% endif %}

src/script_fmt/verilator_sh.tera

@@ -0,0 +1,6 @@
+{% for group in srcs %}{% if group.file_type == 'verilog' %}
+{% for tmp_arg in vlog_args %}{{ tmp_arg }}
+{% endfor %}{% for define in group.defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}
+{% endfor %}{% for incdir in group.incdirs %}+incdir+{{ incdir | replace(from=root, to='$ROOT') }}
+{% endfor %}{% for file in group.files %}{{ file }}
+{% endfor %}{% endif %}{% endfor %}

src/script_fmt/vivado_tcl.tera

@@ -0,0 +1,28 @@
+# {{ HEADER_AUTOGEN }}
+set ROOT "{{ root }}"
+{% if compilation_mode == 'separate' %}{#                                                               Individual block for each source file group
+#}{% for group in srcs %}add_files -norecurse -fileset [current_fileset] [list \{#                      Add files command #}
+    {% for file in group.files %}{{ file | replace(from=root, to='$ROOT') }} \{#                        Add group's files #}
+{% if not loop.last %}    {% endif %}{% endfor %}]
+{% endfor %}{% else %}{# compilation_mode == 'common' #}{#                                              Common block for all files
+#}{% for file in all_files %}{#                                                                         Loop over all files
+#}{% if loop.first %}add_files -norecurse -fileset [current_fileset] [list \{#                          Add files command #}
+    {% endif %}{{ file | replace(from=root, to='$ROOT') }} \{#                                          Add all files #}
+{% if not loop.last %}    {% endif %}{% if loop.last %}]
+{% endif %}{% endfor %}{% endif %}{#
+#}{% for arg in vivado_filesets %}{#                                                                    Loop over vivado arguments
+#}{% for incdir in all_incdirs %}{#                                                                     Loop over include directories
+#}{% if loop.first %}
+set_property include_dirs [list \
+    {% endif %}{{incdir | replace(from=root, to='$ROOT') }}{%if loop.last %} \{#                        Add all include directories #}
+] [current_fileset{{ arg }}]{#                                                                          Add all arguments #}
+{% else %} \
+    {% endif %}{% endfor %}{% endfor %}{#
+#}{% for arg in vivado_filesets %}{#                                                                    Loop over vivado arguments
+#}{% for define in all_defines %}{#                                                                     Loop over defines
+#}{% if loop.first %}
+set_property verilog_define [list \
+    {% endif %}{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \{#  Add all defines #}
+] [current_fileset{{ arg }}]{#                                                                          Add all arguments #}
+{% else %} \
+    {% endif %}{% endfor %}{% endfor %}