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Rename XSIM ifdefs to XILINX_SIMULATOR #265

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Rename XSIM ifdefs to XILINX_SIMULATOR #265

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4 changes: 2 additions & 2 deletions src/axi_demux.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -625,7 +625,7 @@ module axi_demux #(
// Validate parameters.
// pragma translate_off
`ifndef VERILATOR
`ifndef XSIM
`ifndef XILINX_SIMULATOR
initial begin: validate_params
no_mst_ports: assume (NoMstPorts > 0) else
$fatal(1, "The Number of slaves (NoMstPorts) has to be at least 1");
Expand Down Expand Up @@ -774,7 +774,7 @@ module axi_demux_id_counters #(

// pragma translate_off
`ifndef VERILATOR
`ifndef XSIM
`ifndef XILINX_SIMULATOR
// Validate parameters.
cnt_underflow: assert property(
@(posedge clk_i) disable iff (~rst_ni) (pop_en[i] |=> !overflow)) else
Expand Down
2 changes: 1 addition & 1 deletion src/axi_err_slv.sv
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Expand Up @@ -244,7 +244,7 @@ module axi_err_slv #(

// pragma translate_off
`ifndef VERILATOR
`ifndef XSIM
`ifndef XILINX_SIMULATOR
initial begin
assert (Resp == axi_pkg::RESP_DECERR || Resp == axi_pkg::RESP_SLVERR) else
$fatal(1, "This module may only generate RESP_DECERR or RESP_SLVERR responses!");
Expand Down
6 changes: 3 additions & 3 deletions src/axi_test.sv
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Expand Up @@ -1195,7 +1195,7 @@ package axi_test;
automatic logic [AXI_STRB_WIDTH-1:0] rand_strb, strb_mask;
addr = axi_pkg::beat_addr(aw_beat.ax_addr, aw_beat.ax_size, aw_beat.ax_len,
aw_beat.ax_burst, i);
`ifdef XSIM
`ifdef XILINX_SIMULATOR
// std::randomize(w_beat) may behave differently to w_beat.randomize() wrt. limited ranges
// Keeping alternate implementation for XSIM only
rand_success = std::randomize(w_beat); assert (rand_success);
Expand Down Expand Up @@ -1355,7 +1355,7 @@ package axi_test;
wait (ar_queue.size > 0);
ar_beat = ar_queue.peek();
byte_addr = axi_pkg::aligned_addr(ar_beat.ax_addr, axi_pkg::size_t'($clog2(DW/8)));
`ifdef XSIM
`ifdef XILINX_SIMULATOR
// std::randomize(r_beat) may behave differently to r_beat.randomize() wrt. limited ranges
// Keeping alternate implementation for XSIM only
rand_success = std::randomize(r_beat); assert(rand_success);
Expand Down Expand Up @@ -1455,7 +1455,7 @@ package axi_test;
automatic logic rand_success;
wait (b_wait_cnt > 0 && (aw_queue.size() != 0));
aw_beat = aw_queue.pop_front();
`ifdef XSIM
`ifdef XILINX_SIMULATOR
// std::randomize(b_beat) may behave differently to b_beat.randomize() wrt. limited ranges
// Keeping alternate implementation for XSIM only
rand_success = std::randomize(b_beat); assert (rand_success);
Expand Down
4 changes: 2 additions & 2 deletions src/axi_xbar.sv
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Expand Up @@ -125,7 +125,7 @@ import cf_math_pkg::idx_width;
// make sure that the default slave does not get changed, if there is an unserved Ax
// pragma translate_off
`ifndef VERILATOR
`ifndef XSIM
`ifndef XILINX_SIMULATOR
default disable iff (~rst_ni);
default_aw_mst_port_en: assert property(
@(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_resp_o[i].aw_ready)
Expand Down Expand Up @@ -265,7 +265,7 @@ import cf_math_pkg::idx_width;

// pragma translate_off
`ifndef VERILATOR
`ifndef XSIM
`ifndef XILINX_SIMULATOR
initial begin : check_params
id_slv_req_ports: assert ($bits(slv_ports_req_i[0].aw.id ) == Cfg.AxiIdWidthSlvPorts) else
$fatal(1, $sformatf("Slv_req and aw_chan id width not equal."));
Expand Down
2 changes: 1 addition & 1 deletion test/tb_axi_delayer.sv
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Expand Up @@ -83,7 +83,7 @@ module tb_axi_delayer;
@(posedge clk);
repeat (200) begin
@(posedge clk);
`ifdef XSIM
`ifdef XILINX_SIMULATOR
// std::randomize(ax_beat) may behave differently to ax_beat.randomize() wrt. limited ranges
// Keeping alternate implementation for XSIM only
rand_success = std::randomize(ax_beat); assert(rand_success);
Expand Down
4 changes: 2 additions & 2 deletions test/tb_axi_sim_mem.sv
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Expand Up @@ -85,7 +85,7 @@ module tb_axi_sim_mem #(
drv.reset_master();
wait (rst_n);
// AW
`ifdef XSIM
`ifdef XILINX_SIMULATOR
// std::randomize(aw_beat) may behave differently to aw_beat.randomize() wrt. limited ranges
// Keeping alternate implementation for XSIM only
rand_success = std::randomize(aw_beat); assert (rand_success);
Expand All @@ -100,7 +100,7 @@ module tb_axi_sim_mem #(
drv.send_aw(aw_beat);
// W beats
for (int unsigned i = 0; i <= aw_beat.ax_len; i++) begin
`ifdef XSIM
`ifdef XILINX_SIMULATOR
// std::randomize(w_beat) may behave differently to w_beat.randomize() wrt. limited ranges
// Keeping alternate implementation for XSIM only
rand_success = std::randomize(w_beat); assert (rand_success);
Expand Down