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axi_xbar:test: Update according to changed parameters and ports
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Wolfgang Rönninger committed Feb 1, 2021
1 parent d29eefc commit db2063c
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17 changes: 7 additions & 10 deletions scripts/run_vsim.sh
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Original file line number Diff line number Diff line change
Expand Up @@ -102,16 +102,13 @@ exec_test() {
for MST_ID_USE in 3 5; do
MST_ID=5
for DATA_WIDTH in 64 256; do
for PIPE in 0 1; do
call_vsim tb_axi_xbar -t 1ns -voptargs="+acc" \
-gTbNumMasters=$NUM_MST \
-gTbNumSlaves=$NUM_SLV \
-gTbAxiIdWidthMasters=$MST_ID \
-gTbAxiIdUsed=$MST_ID_USE \
-gTbAxiDataWidth=$DATA_WIDTH \
-gTbPipeline=$PIPE \
-gTbEnAtop=$GEN_ATOP
done
call_vsim tb_axi_xbar -t 1ns -voptargs="+acc" \
-gTbNumMasters=$NUM_MST \
-gTbNumSlaves=$NUM_SLV \
-gTbAxiIdWidthMasters=$MST_ID \
-gTbAxiIdUsed=$MST_ID_USE \
-gTbAxiDataWidth=$DATA_WIDTH \
-gTbEnableAtops=$GEN_ATOP
done
done
done
Expand Down
235 changes: 65 additions & 170 deletions test/tb_axi_xbar.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -40,10 +40,8 @@ module tb_axi_xbar #(
parameter int unsigned TbAxiIdUsed = 32'd3,
/// Data width of the AXI channels.
parameter int unsigned TbAxiDataWidth = 32'd64,
/// Pipeline stages in the xbar itself. (Between Demux and mux)
parameter int unsigned TbPipeline = 32'd1,
/// Eanable ATOP generation
parameter bit TbEnAtop = 1'b1
parameter bit TbEnableAtops = 1'b1
);

// TB timing parameters
Expand All @@ -55,26 +53,20 @@ module tb_axi_xbar #(
localparam int unsigned TbAxiIdWidthSlaves = TbAxiIdWidthMasters + $clog2(TbNumMasters);
localparam int unsigned TbAxiAddrWidth = 32'd32;
localparam int unsigned TbAxiStrbWidth = TbAxiDataWidth / 8;
localparam int unsigned TbAxiUserWidth = 5;
// In the bench can change this variables which are set here freely,
localparam axi_pkg::xbar_cfg_t xbar_cfg = '{
NoSlvPorts: TbNumMasters,
NoMstPorts: TbNumSlaves,
MaxMstTrans: 10,
MaxSlvTrans: 6,
FallThrough: 1'b0,
LatencyMode: axi_pkg::CUT_ALL_AX,
PipelineStages: TbPipeline,
AxiIdWidthSlvPorts: TbAxiIdWidthMasters,
AxiIdUsedSlvPorts: TbAxiIdUsed,
AxiAddrWidth: TbAxiAddrWidth,
AxiDataWidth: TbAxiDataWidth,
NoAddrRules: TbNumSlaves
};
localparam int unsigned TbAxiUserWidth = 32'd5;
// In the bench can change these variables which are set here freely,
// Set all XBAR parameter here, even if they do not change per default.
// Makes sure that they are properly propageted through the interface wrapper.
localparam int unsigned TbSlvPortMaxTxns = 32'd10;
localparam int unsigned TbMstPortMaxTxns = 32'd6;
localparam int unsigned TbFallThrough = 1'b0;
localparam int unsigned TbLatencyMode = axi_pkg::NO_LATENCY;
localparam int unsigned TbNumAddrRules = TbNumSlaves;

typedef logic [TbAxiIdWidthMasters-1:0] id_mst_t;
typedef logic [TbAxiIdWidthSlaves-1:0] id_slv_t;
typedef logic [TbAxiAddrWidth-1:0] addr_t;
typedef axi_pkg::xbar_rule_32_t rule_t; // Has to be the same width as axi addr
typedef axi_pkg::xbar_rule_32_t tb_addr_rule_t; // Has to be the same width as axi addr
typedef logic [TbAxiDataWidth-1:0] data_t;
typedef logic [TbAxiStrbWidth-1:0] strb_t;
typedef logic [TbAxiUserWidth-1:0] user_t;
Expand All @@ -96,11 +88,11 @@ module tb_axi_xbar #(
`AXI_TYPEDEF_RESP_T(slv_resp_t, b_chan_slv_t, r_chan_slv_t)

// Each slave has its own address range:
localparam rule_t [xbar_cfg.NoAddrRules-1:0] AddrMap = addr_map_gen();
localparam tb_addr_rule_t [TbNumAddrRules-1:0] AddrMap = addr_map_gen();

function rule_t [xbar_cfg.NoAddrRules-1:0] addr_map_gen ();
for (int unsigned i = 0; i < xbar_cfg.NoAddrRules; i++) begin
addr_map_gen[i] = rule_t'{
function tb_addr_rule_t [TbNumAddrRules-1:0] addr_map_gen ();
for (int unsigned i = 0; i < TbNumAddrRules; i++) begin
addr_map_gen[i] = tb_addr_rule_t'{
idx: unsigned'(i),
start_addr: i * 32'h0000_2000,
end_addr: (i+1) * 32'h0000_2000,
Expand All @@ -121,7 +113,7 @@ module tb_axi_xbar #(
// Maximum number of read and write transactions in flight
.MAX_READ_TXNS ( 20 ),
.MAX_WRITE_TXNS ( 20 ),
.AXI_ATOPS ( TbEnAtop )
.AXI_ATOPS ( TbEnableAtops )
) axi_rand_master_t;
typedef axi_test::axi_rand_slave #(
// AXI interface parameters
Expand Down Expand Up @@ -158,58 +150,60 @@ module tb_axi_xbar #(
.AXI_DATA_WIDTH ( TbAxiDataWidth ),
.AXI_ID_WIDTH ( TbAxiIdWidthMasters ),
.AXI_USER_WIDTH ( TbAxiUserWidth )
) master [TbNumMasters-1:0] ();
) master [TbNumMasters] ();
AXI_BUS_DV #(
.AXI_ADDR_WIDTH ( TbAxiAddrWidth ),
.AXI_DATA_WIDTH ( TbAxiDataWidth ),
.AXI_ID_WIDTH ( TbAxiIdWidthMasters ),
.AXI_USER_WIDTH ( TbAxiUserWidth )
) master_dv [TbNumMasters-1:0] (clk);
) master_dv [TbNumMasters] (clk);
AXI_BUS_DV #(
.AXI_ADDR_WIDTH ( TbAxiAddrWidth ),
.AXI_DATA_WIDTH ( TbAxiDataWidth ),
.AXI_ID_WIDTH ( TbAxiIdWidthMasters ),
.AXI_USER_WIDTH ( TbAxiUserWidth )
) master_monitor_dv [TbNumMasters-1:0] (clk);
for (genvar i = 0; i < TbNumMasters; i++) begin : gen_conn_dv_masters
) master_monitor_dv [TbNumMasters] (clk);
for (genvar i = 0; unsigned'(i) < TbNumMasters; i++) begin : gen_conn_dv_masters
`AXI_ASSIGN (master[i], master_dv[i])
`AXI_ASSIGN_MONITOR(master_monitor_dv[i], master[i])
`AXI_ASSIGN_TO_REQ(masters_req[i], master[i])
`AXI_ASSIGN_FROM_RESP(master[i], masters_resp[i])
`AXI_ASSIGN_TO_RESP(masters_resp[i], master[i])
end

AXI_BUS #(
.AXI_ADDR_WIDTH ( TbAxiAddrWidth ),
.AXI_DATA_WIDTH ( TbAxiDataWidth ),
.AXI_ID_WIDTH ( TbAxiIdWidthSlaves ),
.AXI_USER_WIDTH ( TbAxiUserWidth )
) slave [TbNumSlaves-1:0] ();
) slave [TbNumSlaves] ();
AXI_BUS_DV #(
.AXI_ADDR_WIDTH ( TbAxiAddrWidth ),
.AXI_DATA_WIDTH ( TbAxiDataWidth ),
.AXI_ID_WIDTH ( TbAxiIdWidthSlaves ),
.AXI_USER_WIDTH ( TbAxiUserWidth )
) slave_dv [TbNumSlaves-1:0](clk);
) slave_dv [TbNumSlaves](clk);
AXI_BUS_DV #(
.AXI_ADDR_WIDTH ( TbAxiAddrWidth ),
.AXI_DATA_WIDTH ( TbAxiDataWidth ),
.AXI_ID_WIDTH ( TbAxiIdWidthSlaves ),
.AXI_USER_WIDTH ( TbAxiUserWidth )
) slave_monitor_dv [TbNumSlaves-1:0](clk);
for (genvar i = 0; i < TbNumSlaves; i++) begin : gen_conn_dv_slaves
) slave_monitor_dv [TbNumSlaves](clk);
for (genvar i = 0; unsigned'(i) < TbNumSlaves; i++) begin : gen_conn_dv_slaves
`AXI_ASSIGN(slave_dv[i], slave[i])
`AXI_ASSIGN_FROM_REQ(slave[i], slaves_req[i])
`AXI_ASSIGN_MONITOR(slave_monitor_dv[i], slave[i])
`AXI_ASSIGN_TO_REQ(slaves_req[i], slave[i])
`AXI_ASSIGN_TO_RESP(slaves_resp[i], slave[i])
end
// -------------------------------
// AXI Rand Masters and Slaves
// -------------------------------
// Masters control simulation run time
for (genvar i = 0; i < TbNumMasters; i++) begin : gen_rand_master
for (genvar i = 0; unsigned'(i) < TbNumMasters; i++) begin : gen_rand_master
initial begin
static axi_rand_master_t axi_rand_master = new ( master_dv[i] );
end_of_sim[i] <= 1'b0;
axi_rand_master.add_memory_region(AddrMap[0].start_addr,
AddrMap[xbar_cfg.NoAddrRules-1].end_addr,
AddrMap[TbNumAddrRules-1].end_addr,
axi_pkg::DEVICE_NONBUFFERABLE);
axi_rand_master.reset();
@(posedge rst_n);
Expand All @@ -218,7 +212,7 @@ module tb_axi_xbar #(
end
end

for (genvar i = 0; i < TbNumSlaves; i++) begin : gen_rand_slave
for (genvar i = 0; unsigned'(i) < TbNumSlaves; i++) begin : gen_rand_slave
initial begin
static axi_rand_slave_t axi_rand_slave = new( slave_dv[i] );
axi_rand_slave.reset();
Expand All @@ -229,23 +223,23 @@ module tb_axi_xbar #(

initial begin : proc_monitor
static tb_axi_xbar_pkg::axi_xbar_monitor #(
.AxiAddrWidth ( TbAxiAddrWidth ),
.AxiDataWidth ( TbAxiDataWidth ),
.AxiIdWidthMasters ( TbAxiIdWidthMasters ),
.AxiIdWidthSlaves ( TbAxiIdWidthSlaves ),
.AxiUserWidth ( TbAxiUserWidth ),
.NoMasters ( TbNumMasters ),
.NoSlaves ( TbNumSlaves ),
.NoAddrRules ( xbar_cfg.NoAddrRules ),
.rule_t ( rule_t ),
.AddrMap ( AddrMap ),
.TimeTest ( TestTime )
.AddrWidth ( TbAxiAddrWidth ),
.DataWidth ( TbAxiDataWidth ),
.SlvPortIdWidth ( TbAxiIdWidthMasters ),
.MstPortIdWidth ( TbAxiIdWidthSlaves ),
.UserWidth ( TbAxiUserWidth ),
.NumSlvPorts ( TbNumMasters ),
.NumMstPorts ( TbNumSlaves ),
.NumAddrRules ( TbNumAddrRules ),
.rule_t ( tb_addr_rule_t ),
.AddrMap ( AddrMap ),
.TestTime ( TestTime )
) monitor = new( master_monitor_dv, slave_monitor_dv );
fork
monitor.run();
do begin
#TestTime;
if(end_of_sim == '1) begin
if (end_of_sim == '1) begin
monitor.print_result();
$stop();
end
Expand All @@ -268,37 +262,34 @@ module tb_axi_xbar #(
//-----------------------------------
// DUT
//-----------------------------------
axi_xbar #(
.Cfg ( xbar_cfg ),
.slv_aw_chan_t( aw_chan_mst_t ),
.mst_aw_chan_t( aw_chan_slv_t ),
.w_chan_t ( w_chan_t ),
.slv_b_chan_t ( b_chan_mst_t ),
.mst_b_chan_t ( b_chan_slv_t ),
.slv_ar_chan_t( ar_chan_mst_t ),
.mst_ar_chan_t( ar_chan_slv_t ),
.slv_r_chan_t ( r_chan_mst_t ),
.mst_r_chan_t ( r_chan_slv_t ),
.slv_req_t ( mst_req_t ),
.slv_resp_t ( mst_resp_t ),
.mst_req_t ( slv_req_t ),
.mst_resp_t ( slv_resp_t ),
.rule_t ( rule_t )
axi_xbar_intf #(
.NumSlvPorts ( TbNumMasters ),
.NumMstPorts ( TbNumSlaves ),
.SlvPortIdWidth ( TbAxiIdWidthMasters ),
.SlvPortIdWidthUsed ( TbAxiIdUsed ),
.AddrWidth ( TbAxiAddrWidth ),
.DataWidth ( TbAxiDataWidth ),
.UserWidth ( TbAxiUserWidth ),
.SlvPortMaxTxns ( TbSlvPortMaxTxns ),
.MstPortMaxTxns ( TbMstPortMaxTxns ),
.FallThrough ( TbFallThrough ),
.LatencyMode ( TbLatencyMode ),
.NumAddrRules ( TbNumAddrRules ),
.EnableAtops ( TbEnableAtops ),
.rule_t ( tb_addr_rule_t )
) i_xbar_dut (
.clk_i ( clk ),
.rst_ni ( rst_n ),
.test_i ( 1'b0 ),
.slv_ports_req_i ( masters_req ),
.slv_ports_resp_o ( masters_resp ),
.mst_ports_req_o ( slaves_req ),
.mst_ports_resp_i ( slaves_resp ),
.slv_ports ( master ),
.mst_ports ( slave ),
.addr_map_i ( AddrMap ),
.en_default_mst_port_i ( '0 ),
.default_mst_port_i ( '0 )
.default_mst_ports_i ( '0 )
);

// logger for master modules
for (genvar i = 0; i < TbNumMasters; i++) begin : gen_master_logger
for (genvar i = 0; unsigned'(i) < TbNumMasters; i++) begin : gen_master_logger
axi_chan_logger #(
.TestTime ( TestTime ), // Time after clock, where sampling happens
.LoggerName( $sformatf("axi_logger_master_%0d", i)),
Expand Down Expand Up @@ -334,7 +325,7 @@ module tb_axi_xbar #(
);
end
// logger for slave modules
for (genvar i = 0; i < TbNumSlaves; i++) begin : gen_slave_logger
for (genvar i = 0; unsigned'(i) < TbNumSlaves; i++) begin : gen_slave_logger
axi_chan_logger #(
.TestTime ( TestTime ), // Time after clock, where sampling happens
.LoggerName( $sformatf("axi_logger_slave_%0d",i)),
Expand Down Expand Up @@ -369,100 +360,4 @@ module tb_axi_xbar #(
.r_ready_i ( slaves_req[i].r_ready )
);
end


for (genvar i = 0; i < TbNumMasters; i++) begin : gen_connect_master_monitor
assign master_monitor_dv[i].aw_id = master[i].aw_id ;
assign master_monitor_dv[i].aw_addr = master[i].aw_addr ;
assign master_monitor_dv[i].aw_len = master[i].aw_len ;
assign master_monitor_dv[i].aw_size = master[i].aw_size ;
assign master_monitor_dv[i].aw_burst = master[i].aw_burst ;
assign master_monitor_dv[i].aw_lock = master[i].aw_lock ;
assign master_monitor_dv[i].aw_cache = master[i].aw_cache ;
assign master_monitor_dv[i].aw_prot = master[i].aw_prot ;
assign master_monitor_dv[i].aw_qos = master[i].aw_qos ;
assign master_monitor_dv[i].aw_region = master[i].aw_region;
assign master_monitor_dv[i].aw_atop = master[i].aw_atop ;
assign master_monitor_dv[i].aw_user = master[i].aw_user ;
assign master_monitor_dv[i].aw_valid = master[i].aw_valid ;
assign master_monitor_dv[i].aw_ready = master[i].aw_ready ;
assign master_monitor_dv[i].w_data = master[i].w_data ;
assign master_monitor_dv[i].w_strb = master[i].w_strb ;
assign master_monitor_dv[i].w_last = master[i].w_last ;
assign master_monitor_dv[i].w_user = master[i].w_user ;
assign master_monitor_dv[i].w_valid = master[i].w_valid ;
assign master_monitor_dv[i].w_ready = master[i].w_ready ;
assign master_monitor_dv[i].b_id = master[i].b_id ;
assign master_monitor_dv[i].b_resp = master[i].b_resp ;
assign master_monitor_dv[i].b_user = master[i].b_user ;
assign master_monitor_dv[i].b_valid = master[i].b_valid ;
assign master_monitor_dv[i].b_ready = master[i].b_ready ;
assign master_monitor_dv[i].ar_id = master[i].ar_id ;
assign master_monitor_dv[i].ar_addr = master[i].ar_addr ;
assign master_monitor_dv[i].ar_len = master[i].ar_len ;
assign master_monitor_dv[i].ar_size = master[i].ar_size ;
assign master_monitor_dv[i].ar_burst = master[i].ar_burst ;
assign master_monitor_dv[i].ar_lock = master[i].ar_lock ;
assign master_monitor_dv[i].ar_cache = master[i].ar_cache ;
assign master_monitor_dv[i].ar_prot = master[i].ar_prot ;
assign master_monitor_dv[i].ar_qos = master[i].ar_qos ;
assign master_monitor_dv[i].ar_region = master[i].ar_region;
assign master_monitor_dv[i].ar_user = master[i].ar_user ;
assign master_monitor_dv[i].ar_valid = master[i].ar_valid ;
assign master_monitor_dv[i].ar_ready = master[i].ar_ready ;
assign master_monitor_dv[i].r_id = master[i].r_id ;
assign master_monitor_dv[i].r_data = master[i].r_data ;
assign master_monitor_dv[i].r_resp = master[i].r_resp ;
assign master_monitor_dv[i].r_last = master[i].r_last ;
assign master_monitor_dv[i].r_user = master[i].r_user ;
assign master_monitor_dv[i].r_valid = master[i].r_valid ;
assign master_monitor_dv[i].r_ready = master[i].r_ready ;
end
for (genvar i = 0; i < TbNumSlaves; i++) begin : gen_connect_slave_monitor
assign slave_monitor_dv[i].aw_id = slave[i].aw_id ;
assign slave_monitor_dv[i].aw_addr = slave[i].aw_addr ;
assign slave_monitor_dv[i].aw_len = slave[i].aw_len ;
assign slave_monitor_dv[i].aw_size = slave[i].aw_size ;
assign slave_monitor_dv[i].aw_burst = slave[i].aw_burst ;
assign slave_monitor_dv[i].aw_lock = slave[i].aw_lock ;
assign slave_monitor_dv[i].aw_cache = slave[i].aw_cache ;
assign slave_monitor_dv[i].aw_prot = slave[i].aw_prot ;
assign slave_monitor_dv[i].aw_qos = slave[i].aw_qos ;
assign slave_monitor_dv[i].aw_region = slave[i].aw_region;
assign slave_monitor_dv[i].aw_atop = slave[i].aw_atop ;
assign slave_monitor_dv[i].aw_user = slave[i].aw_user ;
assign slave_monitor_dv[i].aw_valid = slave[i].aw_valid ;
assign slave_monitor_dv[i].aw_ready = slave[i].aw_ready ;
assign slave_monitor_dv[i].w_data = slave[i].w_data ;
assign slave_monitor_dv[i].w_strb = slave[i].w_strb ;
assign slave_monitor_dv[i].w_last = slave[i].w_last ;
assign slave_monitor_dv[i].w_user = slave[i].w_user ;
assign slave_monitor_dv[i].w_valid = slave[i].w_valid ;
assign slave_monitor_dv[i].w_ready = slave[i].w_ready ;
assign slave_monitor_dv[i].b_id = slave[i].b_id ;
assign slave_monitor_dv[i].b_resp = slave[i].b_resp ;
assign slave_monitor_dv[i].b_user = slave[i].b_user ;
assign slave_monitor_dv[i].b_valid = slave[i].b_valid ;
assign slave_monitor_dv[i].b_ready = slave[i].b_ready ;
assign slave_monitor_dv[i].ar_id = slave[i].ar_id ;
assign slave_monitor_dv[i].ar_addr = slave[i].ar_addr ;
assign slave_monitor_dv[i].ar_len = slave[i].ar_len ;
assign slave_monitor_dv[i].ar_size = slave[i].ar_size ;
assign slave_monitor_dv[i].ar_burst = slave[i].ar_burst ;
assign slave_monitor_dv[i].ar_lock = slave[i].ar_lock ;
assign slave_monitor_dv[i].ar_cache = slave[i].ar_cache ;
assign slave_monitor_dv[i].ar_prot = slave[i].ar_prot ;
assign slave_monitor_dv[i].ar_qos = slave[i].ar_qos ;
assign slave_monitor_dv[i].ar_region = slave[i].ar_region;
assign slave_monitor_dv[i].ar_user = slave[i].ar_user ;
assign slave_monitor_dv[i].ar_valid = slave[i].ar_valid ;
assign slave_monitor_dv[i].ar_ready = slave[i].ar_ready ;
assign slave_monitor_dv[i].r_id = slave[i].r_id ;
assign slave_monitor_dv[i].r_data = slave[i].r_data ;
assign slave_monitor_dv[i].r_resp = slave[i].r_resp ;
assign slave_monitor_dv[i].r_last = slave[i].r_last ;
assign slave_monitor_dv[i].r_user = slave[i].r_user ;
assign slave_monitor_dv[i].r_valid = slave[i].r_valid ;
assign slave_monitor_dv[i].r_ready = slave[i].r_ready ;
end
endmodule
endmodule : tb_axi_xbar
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