axi_to_mem: propagate parameter for output fifo depth

pulp-platform · Sep 28, 2022 · ccc7e34 · ccc7e34
1 parent 686b359
commit ccc7e34
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Showing 4 changed files with 85 additions and 63 deletions.
diff --git a/src/axi_to_mem.sv b/src/axi_to_mem.sv
@@ -34,6 +34,8 @@ module axi_to_mem #(
   parameter int unsigned BufDepth   = 1,
   /// Hide write requests if the strb == '0
   parameter bit          HideStrb   = 1'b0,
+  /// Depth of output fifo/fall_through_register. Increase for asymmetric backpressure (contention) on banks.
+  parameter int unsigned OutFifoDepth = 1,
   /// Dependent parameter, do not override. Memory address type.
   localparam type addr_t     = logic [AddrWidth-1:0],
   /// Dependent parameter, do not override. Memory data type.
@@ -348,12 +350,12 @@ module axi_to_mem #(
 
   // Split single memory request to desired number of banks.
   mem_to_banks #(
-    .AddrWidth  ( AddrWidth ),
-    .DataWidth  ( DataWidth ),
-    .NumBanks   ( NumBanks  ),
-    .HideStrb   ( HideStrb  ),
-    .MaxTrans   ( BufDepth  ),
-    .FifoDepth  ( 2         )
+    .AddrWidth ( AddrWidth    ),
+    .DataWidth ( DataWidth    ),
+    .NumBanks  ( NumBanks     ),
+    .HideStrb  ( HideStrb     ),
+    .MaxTrans  ( BufDepth     ),
+    .FifoDepth ( OutFifoDepth )
   ) i_mem_to_banks (
     .clk_i,
     .rst_ni,
@@ -464,19 +466,21 @@ endmodule
 /// Interface wrapper for module `axi_to_mem`.
 module axi_to_mem_intf #(
   /// See `axi_to_mem`, parameter `AddrWidth`.
-  parameter int unsigned ADDR_WIDTH = 32'd0,
+  parameter int unsigned ADDR_WIDTH     = 32'd0,
   /// See `axi_to_mem`, parameter `DataWidth`.
-  parameter int unsigned DATA_WIDTH = 32'd0,
+  parameter int unsigned DATA_WIDTH     = 32'd0,
   /// AXI4+ATOP ID width.
-  parameter int unsigned ID_WIDTH   = 32'd0,
+  parameter int unsigned ID_WIDTH       = 32'd0,
   /// AXI4+ATOP user width.
-  parameter int unsigned USER_WIDTH = 32'd0,
+  parameter int unsigned USER_WIDTH     = 32'd0,
   /// See `axi_to_mem`, parameter `NumBanks`.
-  parameter int unsigned NUM_BANKS  = 32'd0,
+  parameter int unsigned NUM_BANKS      = 32'd0,
   /// See `axi_to_mem`, parameter `BufDepth`.
-  parameter int unsigned BUF_DEPTH  = 32'd1,
+  parameter int unsigned BUF_DEPTH      = 32'd1,
   /// Hide write requests if the strb == '0
-  parameter bit          HIDE_STRB  = 1'b0,
+  parameter bit          HIDE_STRB      = 1'b0,
+  /// Depth of output fifo/fall_through_register. Increase for asymmetric backpressure (contention) on banks.
+  parameter int unsigned OUT_FIFO_DEPTH = 32'd1,
   /// Dependent parameter, do not override. See `axi_to_mem`, parameter `addr_t`.
   localparam type addr_t     = logic [ADDR_WIDTH-1:0],
   /// Dependent parameter, do not override. See `axi_to_mem`, parameter `mem_data_t`.
@@ -527,14 +531,15 @@ module axi_to_mem_intf #(
   `AXI_ASSIGN_TO_REQ(req, slv)
   `AXI_ASSIGN_FROM_RESP(slv, resp)
   axi_to_mem #(
-    .axi_req_t  ( req_t     ),
-    .axi_resp_t ( resp_t    ),
-    .AddrWidth  ( ADDR_WIDTH ),
-    .DataWidth  ( DATA_WIDTH ),
-    .IdWidth    ( ID_WIDTH   ),
-    .NumBanks   ( NUM_BANKS  ),
-    .BufDepth   ( BUF_DEPTH  ),
-    .HideStrb   ( HIDE_STRB  )
+    .axi_req_t    ( req_t          ),
+    .axi_resp_t   ( resp_t         ),
+    .AddrWidth    ( ADDR_WIDTH     ),
+    .DataWidth    ( DATA_WIDTH     ),
+    .IdWidth      ( ID_WIDTH       ),
+    .NumBanks     ( NUM_BANKS      ),
+    .BufDepth     ( BUF_DEPTH      ),
+    .HideStrb     ( HIDE_STRB      ),
+    .OutFifoDepth ( OUT_FIFO_DEPTH )
   ) i_axi_to_mem (
     .clk_i,
     .rst_ni,

diff --git a/src/axi_to_mem_banked.sv b/src/axi_to_mem_banked.sv
@@ -53,6 +53,8 @@ module axi_to_mem_banked #(
   parameter int unsigned                  MemLatency    = 32'd1,
   /// Hide write requests if the strb == '0
   parameter bit                           HideStrb      = 1'b0,
+  /// Depth of output fifo/fall_through_register. Increase for asymmetric backpressure (contention) on banks.
+  parameter int unsigned                  OutFifoDepth = 1,
   /// DEPENDENT PARAMETER, DO NOT OVERWRITE! Address type of the memory request.
   parameter type mem_addr_t = logic [MemAddrWidth-1:0],
   /// DEPENDENT PARAMETER, DO NOT OVERWRITE! Atomic operation type for the memory request.
@@ -183,14 +185,15 @@ module axi_to_mem_banked #(
     // Careful, request / grant
     // Only assert grant, if there is a ready
     axi_to_mem #(
-      .axi_req_t ( axi_req_t          ),
-      .axi_resp_t( axi_resp_t         ),
-      .AddrWidth ( AxiAddrWidth       ),
-      .DataWidth ( AxiDataWidth       ),
-      .IdWidth   ( AxiIdWidth         ),
-      .NumBanks  ( BanksPerAxiChannel ),
-      .BufDepth  ( MemLatency         ),
-      .HideStrb  ( HideStrb           )
+      .axi_req_t    ( axi_req_t          ),
+      .axi_resp_t   ( axi_resp_t         ),
+      .AddrWidth    ( AxiAddrWidth       ),
+      .DataWidth    ( AxiDataWidth       ),
+      .IdWidth      ( AxiIdWidth         ),
+      .NumBanks     ( BanksPerAxiChannel ),
+      .BufDepth     ( MemLatency         ),
+      .HideStrb     ( HideStrb           ),
+      .OutFifoDepth ( OutFifoDepth       )
     ) i_axi_to_mem (
       .clk_i,
       .rst_ni,
@@ -331,6 +334,8 @@ module axi_to_mem_banked_intf #(
   parameter int unsigned                  MEM_LATENCY    = 32'd1,
   /// Hide write requests if the strb == '0
   parameter bit                           HIDE_STRB      = 1'b0,
+  /// Depth of output fifo/fall_through_register. Increase for asymmetric backpressure (contention) on banks.
+  parameter int unsigned                  OUT_FIFO_DEPTH = 32'd1,
   // DEPENDENT PARAMETERS, DO NOT OVERWRITE!
   parameter type mem_addr_t = logic [MEM_ADDR_WIDTH-1:0],
   parameter type mem_atop_t = logic [5:0],
@@ -398,7 +403,8 @@ module axi_to_mem_banked_intf #(
     .MemAddrWidth  ( MEM_ADDR_WIDTH             ),
     .MemDataWidth  ( MEM_DATA_WIDTH             ),
     .MemLatency    ( MEM_LATENCY                ),
-    .HideStrb      ( HIDE_STRB                  )
+    .HideStrb      ( HIDE_STRB                  ),
+    .OutFifoDepth  ( OUT_FIFO_DEPTH             )
   ) i_axi_to_mem_banked (
     .clk_i,
     .rst_ni,

diff --git a/src/axi_to_mem_interleaved.sv b/src/axi_to_mem_interleaved.sv
@@ -34,6 +34,8 @@ module axi_to_mem_interleaved #(
   parameter int unsigned BufDepth   = 1,
   /// Hide write requests if the strb == '0
   parameter bit          HideStrb   = 1'b0,
+  /// Depth of output fifo/fall_through_register. Increase for asymmetric backpressure (contention) on banks.
+  parameter int unsigned OutFifoDepth = 1,
   /// Dependent parameter, do not override. Memory address type.
   parameter type addr_t     = logic [AddrWidth-1:0],
   /// Dependent parameter, do not override. Memory data type.
@@ -115,14 +117,15 @@ module axi_to_mem_interleaved #(
   end
 
   axi_to_mem #(
-    .axi_req_t   ( axi_req_t  ),
-    .axi_resp_t  ( axi_resp_t ),
-    .AddrWidth   ( AddrWidth  ),
-    .DataWidth   ( DataWidth  ),
-    .IdWidth     ( IdWidth    ),
-    .NumBanks    ( NumBanks   ),
-    .BufDepth    ( BufDepth   ),
-    .HideStrb    ( HideStrb   )
+    .axi_req_t   ( axi_req_t    ),
+    .axi_resp_t  ( axi_resp_t   ),
+    .AddrWidth   ( AddrWidth    ),
+    .DataWidth   ( DataWidth    ),
+    .IdWidth     ( IdWidth      ),
+    .NumBanks    ( NumBanks     ),
+    .BufDepth    ( BufDepth     ),
+    .HideStrb    ( HideStrb     ),
+    .OutFifoDepth( OutFifoDepth )
   ) i_axi_to_mem_write (
     .clk_i        ( clk_i         ),
     .rst_ni       ( rst_ni        ),
@@ -141,14 +144,15 @@ module axi_to_mem_interleaved #(
   );
 
   axi_to_mem #(
-    .axi_req_t   ( axi_req_t  ),
-    .axi_resp_t  ( axi_resp_t ),
-    .AddrWidth   ( AddrWidth  ),
-    .DataWidth   ( DataWidth  ),
-    .IdWidth     ( IdWidth    ),
-    .NumBanks    ( NumBanks   ),
-    .BufDepth    ( BufDepth   ),
-    .HideStrb    ( HideStrb   )
+    .axi_req_t    ( axi_req_t    ),
+    .axi_resp_t   ( axi_resp_t   ),
+    .AddrWidth    ( AddrWidth    ),
+    .DataWidth    ( DataWidth    ),
+    .IdWidth      ( IdWidth      ),
+    .NumBanks     ( NumBanks     ),
+    .BufDepth     ( BufDepth     ),
+    .HideStrb     ( HideStrb     ),
+    .OutFifoDepth ( OutFifoDepth )
   ) i_axi_to_mem_read (
     .clk_i        ( clk_i         ),
     .rst_ni       ( rst_ni        ),

diff --git a/src/axi_to_mem_split.sv b/src/axi_to_mem_split.sv
@@ -34,6 +34,8 @@ module axi_to_mem_split #(
   parameter int unsigned BufDepth     = 0,
   /// Hide write requests if the strb == '0
   parameter bit          HideStrb   = 1'b0,
+  /// Depth of output fifo/fall_through_register. Increase for asymmetric backpressure (contention) on banks.
+  parameter int unsigned OutFifoDepth = 1,
   /// Dependent parameters, do not override. Number of memory ports.
   parameter int unsigned NumMemPorts  = 2*AxiDataWidth/MemDataWidth,
   /// Dependent parameter, do not override. Memory address type.
@@ -104,14 +106,15 @@ module axi_to_mem_split #(
   assign busy_o = read_busy || write_busy;
 
   axi_to_mem #(
-    .axi_req_t  ( axi_req_t     ),
-    .axi_resp_t ( axi_resp_t    ),
-    .AddrWidth  ( AddrWidth     ),
-    .DataWidth  ( AxiDataWidth  ),
-    .IdWidth    ( IdWidth       ),
-    .NumBanks   ( NumMemPorts/2 ),
-    .BufDepth   ( BufDepth      ),
-    .HideStrb   ( 1'b0          )
+    .axi_req_t    ( axi_req_t     ),
+    .axi_resp_t   ( axi_resp_t    ),
+    .AddrWidth    ( AddrWidth     ),
+    .DataWidth    ( AxiDataWidth  ),
+    .IdWidth      ( IdWidth       ),
+    .NumBanks     ( NumMemPorts/2 ),
+    .BufDepth     ( BufDepth      ),
+    .HideStrb     ( 1'b0          ),
+    .OutFifoDepth ( OutFifoDepth  )
   ) i_axi_to_mem_read (
     .clk_i,
     .rst_ni,
@@ -130,14 +133,15 @@ module axi_to_mem_split #(
   );
 
   axi_to_mem #(
-    .axi_req_t  ( axi_req_t     ),
-    .axi_resp_t ( axi_resp_t    ),
-    .AddrWidth  ( AddrWidth     ),
-    .DataWidth  ( AxiDataWidth  ),
-    .IdWidth    ( IdWidth       ),
-    .NumBanks   ( NumMemPorts/2 ),
-    .BufDepth   ( BufDepth      ),
-    .HideStrb   ( HideStrb      )
+    .axi_req_t    ( axi_req_t     ),
+    .axi_resp_t   ( axi_resp_t    ),
+    .AddrWidth    ( AddrWidth     ),
+    .DataWidth    ( AxiDataWidth  ),
+    .IdWidth      ( IdWidth       ),
+    .NumBanks     ( NumMemPorts/2 ),
+    .BufDepth     ( BufDepth      ),
+    .HideStrb     ( HideStrb      ),
+    .OutFifoDepth ( OutFifoDepth  )
   ) i_axi_to_mem_write (
     .clk_i,
     .rst_ni,
@@ -174,6 +178,8 @@ module axi_to_mem_split_intf #(
   parameter int unsigned BUF_DEPTH      = 0,
   /// Hide write requests if the strb == '0
   parameter bit          HIDE_STRB      = 1'b0,
+  /// Depth of output fifo/fall_through_register. Increase for asymmetric backpressure (contention) on banks.
+  parameter int unsigned OUT_FIFO_DEPTH = 32'd1,
   /// Dependent parameters, do not override. Number of memory ports.
   parameter int unsigned NUM_MEM_PORTS  = 2*AXI_DATA_WIDTH/MEM_DATA_WIDTH,
   /// Dependent parameter, do not override. See `axi_to_mem`, parameter `addr_t`.
@@ -230,7 +236,8 @@ module axi_to_mem_split_intf #(
     .IdWidth      ( AXI_ID_WIDTH   ),
     .MemDataWidth ( MEM_DATA_WIDTH ), // must divide `AxiDataWidth` without remainder
     .BufDepth     ( BUF_DEPTH      ),
-    .HideStrb     ( HIDE_STRB      )
+    .HideStrb     ( HIDE_STRB      ),
+    .OutFifoDepth ( OUT_FIFO_DEPTH )
   ) i_axi_to_mem_split (
     .clk_i,
     .rst_ni,