README: Link to paper PDF instead of abstract

README.md

@@ -12,7 +12,7 @@ Our **design goals** are:
 - **Full AXI Standard Compliance**.
 - **Compatibility** with a [wide range of (recent versions of) EDA tools](#which-eda-tools-are-supported) and implementation in standardized synthesizable SystemVerilog.
 
-The **design and microarchitecture** of the modules in this repository is described in [**this paper**](https://ieeexplore.ieee.org/document/9522037) ([preprint](https://arxiv.org/abs/2009.05334)).  If you use our work in your research, please cite it.
+The **design and microarchitecture** of the modules in this repository is described in [**this paper**](https://ieeexplore.ieee.org/document/9522037) ([preprint](https://arxiv.org/pdf/2009.05334)).  If you use our work in your research, please cite it.
 
 
 ## List of Modules