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util: Improvements for benchmarking #84

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merged 10 commits into from
Dec 10, 2024
Merged

util: Improvements for benchmarking #84

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ce7aa79
util(jobs): Set random seed for reproducability
fischeti Nov 21, 2024
12ace34
util(jobs): Rename traffic patterns to common names used in literature
fischeti Nov 21, 2024
fd97c97
tb(mesh): Fix XY indexing and genvar loops
fischeti Nov 21, 2024
27a77ac
tb(mesh): Add AXI Fifo in front of monitors
fischeti Nov 21, 2024
aca9ed0
test(dma): Support specifying an injection ratio of the DMA model
fischeti Nov 21, 2024
65c288d
test: Add `IdealSlave` for benchmarking
fischeti Nov 21, 2024
e78b39e
util(jobs): Add new `matmul` pattern
fischeti Dec 6, 2024
dd29796
git: Update .gitignore
fischeti Dec 6, 2024
c7f7eba
hw(nw_join): Use `parameter` instead of `localparam`
fischeti Dec 6, 2024
b7dc470
lint: Python sources
fischeti Dec 10, 2024
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1 change: 1 addition & 0 deletions .gitignore
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Expand Up @@ -89,6 +89,7 @@ scripts/spyglass/*

# experiment outputs
util/output/*
measurements

# Misc
*.csv
Expand Down
2 changes: 1 addition & 1 deletion .gitlab-ci.yml
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Expand Up @@ -111,7 +111,7 @@ run-traffic:
matrix:
- DUT: [axi_mesh, nw_mesh]
ROUTE_ALGO: [xy, src, id]
TRAFFIC_TYPE: [random, hbm, shuffle, single_dest_center]
TRAFFIC_TYPE: [uniform, hbm, shuffle, hotspot]
TRAFFIC_RW: [read, write]
script:
- make jobs
Expand Down
3 changes: 3 additions & 0 deletions Makefile
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Expand Up @@ -67,6 +67,9 @@ VCS_ARGS += -j 8
ifdef JOB_NAME
VSIM_FLAGS += +JOB_NAME=$(JOB_NAME)
endif
ifdef TRAFFIC_INJ_RATIO
VSIM_FLAGS += +TRAFFIC_INJ_RATIO=$(TRAFFIC_INJ_RATIO)
endif
ifdef JOB_DIR
VSIM_FLAGS += +JOB_DIR=$(JOB_DIR)
endif
Expand Down
6 changes: 3 additions & 3 deletions hw/floo_nw_join.sv
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Expand Up @@ -28,9 +28,9 @@ module floo_nw_join #(
/// max(`AxiNarrowIdWidth` and `AxiWideIdWidth`) == AxidOutWidth - 1
parameter int unsigned AxiIdOutWidth = AxiCfgJoin.InIdWidth,
/// ID width of the busses before muxing them together.
localparam int unsigned AxiIdConvWidth = AxiIdOutWidth - 1,
parameter int unsigned AxiIdConvWidth = AxiIdOutWidth - 1,
/// Default parameter for number of inflight narrow transactions
localparam int unsigned AxiNarrowMaxTxns = 8,
parameter int unsigned AxiNarrowMaxTxns = 8,
/// Maximum number of in-flight AXI narrow write transactions
parameter int unsigned AxiNarrowMaxWriteTxns = AxiNarrowMaxTxns,
/// Maximum number of in-flight AXI narrow read transactions
Expand All @@ -46,7 +46,7 @@ module floo_nw_join #(
/// Maximum number of in-flight transactions with the same ID at the narrow master port.
parameter int unsigned AxiNarrowMstPortMaxTxnsPerId = AxiNarrowMaxTxns,
/// Default parameter for number of inflight wide transactions
localparam int unsigned AxiWideMaxTxns = 32,
parameter int unsigned AxiWideMaxTxns = 32,
/// Maximum number of in-flight AXI wide write transactions
parameter int unsigned AxiWideMaxWriteTxns = AxiWideMaxTxns,
/// Number of unique IDs on the wide AXI bus
Expand Down
50 changes: 39 additions & 11 deletions hw/tb/tb_floo_axi_mesh.sv
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Expand Up @@ -21,6 +21,10 @@ module tb_floo_axi_mesh;
localparam int unsigned NumHBMChannels = NumY;
localparam int unsigned NumMax = (NumX > NumY) ? NumX : NumY;

// Add a buffer before the AXI monitors. Otherwise transactions
// are stalled which skews the latency measurements
localparam int unsigned FifoDepth = 100;

typedef axi_in_addr_t addr_t;
localparam int unsigned HBMLatency = 100;
localparam addr_t HBMSize = 48'h10000; // 64KB
Expand Down Expand Up @@ -49,6 +53,10 @@ module tb_floo_axi_mesh;
axi_out_req_t [NumHBMChannels-1:0] hbm_req;
axi_out_rsp_t [NumHBMChannels-1:0] hbm_rsp;

axi_in_req_t [NumX-1:0][NumY-1:0] cluster_in_buf_req;
axi_in_rsp_t [NumX-1:0][NumY-1:0] cluster_in_buf_rsp;


///////////////////
// HBM Model //
///////////////////
Expand Down Expand Up @@ -81,10 +89,10 @@ module tb_floo_axi_mesh;
////////////////////////

for (genvar x = 0; x < NumX; x++) begin : gen_x
for (genvar y = 0; y < NumX; y++) begin : gen_y
for (genvar y = 0; y < NumY; y++) begin : gen_y
localparam string DmaName = $sformatf("dma_%0d_%0d", x, y);

localparam int unsigned Index = x * NumX + y;
localparam int unsigned Index = x * NumY + y;
localparam addr_t MemBaseAddr = Sam[ClusterNi00+Index].start_addr;

floo_dma_test_node #(
Expand All @@ -109,6 +117,26 @@ module tb_floo_axi_mesh;
.end_of_sim_o ( end_of_sim[x][y] )
);

axi_fifo #(
.Depth ( FifoDepth ),
.FallThrough ( 1'b1 ),
.aw_chan_t ( axi_in_aw_chan_t ),
.w_chan_t ( axi_in_w_chan_t ),
.b_chan_t ( axi_in_b_chan_t ),
.ar_chan_t ( axi_in_ar_chan_t ),
.r_chan_t ( axi_in_r_chan_t ),
.axi_req_t ( axi_in_req_t ),
.axi_resp_t ( axi_in_rsp_t )
) i_axi_narrow_buffer (
.clk_i ( clk ),
.rst_ni ( rst_n ),
.test_i ( 1'b0 ),
.slv_req_i ( cluster_in_req[x][y] ),
.slv_resp_o ( cluster_in_rsp[x][y] ),
.mst_req_o ( cluster_in_buf_req[x][y] ),
.mst_resp_i ( cluster_in_buf_rsp[x][y] )
);

axi_bw_monitor #(
.req_t ( axi_in_req_t ),
.rsp_t ( axi_in_rsp_t ),
Expand All @@ -132,15 +160,15 @@ module tb_floo_axi_mesh;
/////////////////////////

floo_axi_mesh_noc i_floo_axi_mesh_noc (
.clk_i ( clk ),
.rst_ni ( rst_n ),
.test_enable_i ( 1'b0 ),
.cluster_axi_in_req_i ( cluster_in_req ),
.cluster_axi_in_rsp_o ( cluster_in_rsp ),
.cluster_axi_out_req_o ( cluster_out_req ),
.cluster_axi_out_rsp_i ( cluster_out_rsp ),
.hbm_axi_out_req_o ( hbm_req ),
.hbm_axi_out_rsp_i ( hbm_rsp )
.clk_i ( clk ),
.rst_ni ( rst_n ),
.test_enable_i ( 1'b0 ),
.cluster_axi_in_req_i ( cluster_in_buf_req ),
.cluster_axi_in_rsp_o ( cluster_in_buf_rsp ),
.cluster_axi_out_req_o ( cluster_out_req ),
.cluster_axi_out_rsp_i ( cluster_out_rsp ),
.hbm_axi_out_req_o ( hbm_req ),
.hbm_axi_out_rsp_i ( hbm_rsp )
);


Expand Down
87 changes: 68 additions & 19 deletions hw/tb/tb_floo_nw_mesh.sv
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Expand Up @@ -21,6 +21,10 @@ module tb_floo_nw_mesh;
localparam int unsigned NumHBMChannels = NumY;
localparam int unsigned NumMax = (NumX > NumY) ? NumX : NumY;

// Add a buffer before the AXI monitors. Otherwise transactions
// are stalled which skews the latency measurements
localparam int unsigned FifoDepth = 100;

typedef axi_narrow_in_addr_t addr_t;
localparam int unsigned HBMLatency = 100;
localparam addr_t HBMSize = 48'h10000; // 64KB
Expand Down Expand Up @@ -55,6 +59,11 @@ module tb_floo_nw_mesh;
axi_wide_out_req_t [NumHBMChannels-1:0] hbm_wide_req;
axi_wide_out_rsp_t [NumHBMChannels-1:0] hbm_wide_rsp;

axi_narrow_in_req_t [NumX-1:0][NumY-1:0] cluster_narrow_in_buf_req;
axi_narrow_in_rsp_t [NumX-1:0][NumY-1:0] cluster_narrow_in_buf_rsp;
axi_wide_in_req_t [NumX-1:0][NumY-1:0] cluster_wide_in_buf_req;
axi_wide_in_rsp_t [NumX-1:0][NumY-1:0] cluster_wide_in_buf_rsp;

///////////////////
// HBM Model //
///////////////////
Expand Down Expand Up @@ -119,11 +128,11 @@ module tb_floo_nw_mesh;
////////////////////////

for (genvar x = 0; x < NumX; x++) begin : gen_x
for (genvar y = 0; y < NumX; y++) begin : gen_y
for (genvar y = 0; y < NumY; y++) begin : gen_y
localparam string NarrowDmaName = $sformatf("narrow_dma_%0d_%0d", x, y);
localparam string WideDmaName = $sformatf("wide_dma_%0d_%0d", x, y);

localparam int unsigned Index = x * NumX + y;
localparam int unsigned Index = x * NumY + y;
localparam addr_t MemBaseAddr = Sam[ClusterNi00+Index].start_addr;

floo_dma_test_node #(
Expand Down Expand Up @@ -170,6 +179,46 @@ module tb_floo_nw_mesh;
.end_of_sim_o ( end_of_sim[x][y][1] )
);

axi_fifo #(
.Depth ( FifoDepth ),
.FallThrough ( 1'b1 ),
.aw_chan_t ( axi_narrow_in_aw_chan_t ),
.w_chan_t ( axi_narrow_in_w_chan_t ),
.b_chan_t ( axi_narrow_in_b_chan_t ),
.ar_chan_t ( axi_narrow_in_ar_chan_t ),
.r_chan_t ( axi_narrow_in_r_chan_t ),
.axi_req_t ( axi_narrow_in_req_t ),
.axi_resp_t ( axi_narrow_in_rsp_t )
) i_axi_narrow_buffer (
.clk_i ( clk ),
.rst_ni ( rst_n ),
.test_i ( 1'b0 ),
.slv_req_i ( cluster_narrow_in_req[x][y] ),
.slv_resp_o ( cluster_narrow_in_rsp[x][y] ),
.mst_req_o ( cluster_narrow_in_buf_req[x][y] ),
.mst_resp_i ( cluster_narrow_in_buf_rsp[x][y] )
);

axi_fifo #(
.Depth ( FifoDepth ),
.FallThrough ( 1'b1 ),
.aw_chan_t ( axi_wide_in_aw_chan_t ),
.w_chan_t ( axi_wide_in_w_chan_t ),
.b_chan_t ( axi_wide_in_b_chan_t ),
.ar_chan_t ( axi_wide_in_ar_chan_t ),
.r_chan_t ( axi_wide_in_r_chan_t ),
.axi_req_t ( axi_wide_in_req_t ),
.axi_resp_t ( axi_wide_in_rsp_t )
) i_axi_wide_buffer (
.clk_i ( clk ),
.rst_ni ( rst_n ),
.test_i ( 1'b0 ),
.slv_req_i ( cluster_wide_in_req[x][y] ),
.slv_resp_o ( cluster_wide_in_rsp[x][y] ),
.mst_req_o ( cluster_wide_in_buf_req[x][y] ),
.mst_resp_i ( cluster_wide_in_buf_rsp[x][y] )
);

axi_bw_monitor #(
.req_t ( axi_narrow_in_req_t ),
.rsp_t ( axi_narrow_in_rsp_t ),
Expand All @@ -183,7 +232,7 @@ module tb_floo_nw_mesh;
.rsp_i ( cluster_narrow_in_rsp[x][y] ),
.ar_in_flight_o ( ),
.aw_in_flight_o ( )
);
);

axi_bw_monitor #(
.req_t ( axi_wide_in_req_t ),
Expand All @@ -198,7 +247,7 @@ module tb_floo_nw_mesh;
.rsp_i ( cluster_wide_in_rsp[x][y] ),
.ar_in_flight_o ( ),
.aw_in_flight_o ( )
);
);
end
end

Expand All @@ -208,21 +257,21 @@ module tb_floo_nw_mesh;
/////////////////////////

floo_nw_mesh_noc i_floo_nw_mesh_noc (
.clk_i ( clk ),
.rst_ni ( rst_n ),
.test_enable_i ( 1'b0 ),
.cluster_narrow_in_req_i ( cluster_narrow_in_req ),
.cluster_narrow_in_rsp_o ( cluster_narrow_in_rsp ),
.cluster_narrow_out_req_o ( cluster_narrow_out_req ),
.cluster_narrow_out_rsp_i ( cluster_narrow_out_rsp ),
.cluster_wide_in_req_i ( cluster_wide_in_req ),
.cluster_wide_in_rsp_o ( cluster_wide_in_rsp ),
.cluster_wide_out_req_o ( cluster_wide_out_req ),
.cluster_wide_out_rsp_i ( cluster_wide_out_rsp ),
.hbm_narrow_out_req_o ( hbm_narrow_req ),
.hbm_narrow_out_rsp_i ( hbm_narrow_rsp ),
.hbm_wide_out_req_o ( hbm_wide_req ),
.hbm_wide_out_rsp_i ( hbm_wide_rsp )
.clk_i ( clk ),
.rst_ni ( rst_n ),
.test_enable_i ( 1'b0 ),
.cluster_narrow_in_req_i ( cluster_narrow_in_buf_req ),
.cluster_narrow_in_rsp_o ( cluster_narrow_in_buf_rsp ),
.cluster_narrow_out_req_o ( cluster_narrow_out_req ),
.cluster_narrow_out_rsp_i ( cluster_narrow_out_rsp ),
.cluster_wide_in_req_i ( cluster_wide_in_buf_req ),
.cluster_wide_in_rsp_o ( cluster_wide_in_buf_rsp ),
.cluster_wide_out_req_o ( cluster_wide_out_req ),
.cluster_wide_out_rsp_i ( cluster_wide_out_rsp ),
.hbm_narrow_out_req_o ( hbm_narrow_req ),
.hbm_narrow_out_rsp_i ( hbm_narrow_rsp ),
.hbm_wide_out_req_o ( hbm_wide_req ),
.hbm_wide_out_rsp_i ( hbm_wide_rsp )
);


Expand Down
21 changes: 19 additions & 2 deletions hw/test/floo_axi_rand_slave.sv
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Expand Up @@ -131,8 +131,15 @@ module floo_axi_rand_slave #(
.UW ( AxiCfg.UserWidth ),
// Stimuli application and test time
.TA ( ApplTime ),
.TT ( TestTime )
) axi_rand_slave_t;
.TT ( TestTime ),
// Responsiveness
.AX_MIN_WAIT_CYCLES (0),
.AX_MAX_WAIT_CYCLES (0),
.R_MIN_WAIT_CYCLES (0),
.R_MAX_WAIT_CYCLES (0),
.RESP_MIN_WAIT_CYCLES (0),
.RESP_MAX_WAIT_CYCLES (0)
) axi_rand_ideal_slave_t;

typedef axi_test::axi_rand_slave #(
// AXI interface parameters
Expand Down Expand Up @@ -173,6 +180,7 @@ module floo_axi_rand_slave #(
// axi slave
axi_rand_slow_slave_t axi_rand_slow_slave[NumSlaves];
axi_rand_fast_slave_t axi_rand_fast_slave[NumSlaves];
axi_rand_ideal_slave_t axi_rand_ideal_slave[NumSlaves];

if (SlaveType == floo_test_pkg::SlowSlave) begin : gen_slow_slaves
for (genvar i = 0; i < NumSlaves; i++) begin : gen_slow_slaves
Expand All @@ -192,6 +200,15 @@ module floo_axi_rand_slave #(
axi_rand_fast_slave[i].run();
end
end
end else if (SlaveType == floo_test_pkg::IdealSlave) begin : gen_fast_slaves
for (genvar i = 0; i < NumSlaves; i++) begin : gen_fast_slaves
initial begin
axi_rand_ideal_slave[i] = new( slave_dv[i] );
axi_rand_ideal_slave[i].reset();
@(posedge rst_ni)
axi_rand_ideal_slave[i].run();
end
end
end else if (SlaveType == floo_test_pkg::MixedSlave) begin : gen_mixed_slaves
for (genvar i = 0; i < NumSlaves; i++) begin : gen_mixed_slaves
if (i % 2 == 0) begin : gen_slow_slaves
Expand Down
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