verif: Traffic testbench fixes and enhancements

.gitlab-ci.yml

@@ -67,6 +67,23 @@ run-vsim:
       when: manual
     - when: always
 
+run-traffic:
+  stage: run
+  variables:
+    VSIM_TB_DUT: tb_floo_dma_mesh
+    JOB_NAME: mesh
+  parallel:
+    matrix:
+      - TRAFFIC_TYPE: [random, hbm, onehop]
+        TRAFFIC_RW: [read, write]
+  needs:
+    - collect-bender-sources
+    - compile-vsim
+  script:
+    - make jobs
+    - make run-sim-batch | tee vsim.log 2>&1
+    - 'grep "Errors: 0," vsim.log'
+
 morty:
   stage: build
   script:

CHANGELOG.md

@@ -9,6 +9,15 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
 ### Added
 
 - Added Chimney Parameters `EnMgrPort` and `EnSbrPort` to properly parametrize Manager resp. Subordinate-only instances of a chimney
+- Added `XYRouteOpt` parameter to router to enable/disable routing optimizations when using `XYRouting`
+
+### Changed
+
+- Removed `xy_id_i` ports from AXI chimneys in favor of a generic `id_i` port for both `IdTable` and `XYRouting`
+
+### Fixed
+
+- Fixed missing backpressure in the `NoRoB` version of the reorder buffer, which could lead to overflow of counters
 
 ## [0.2.1] - 2023-10-13
 

Makefile

@@ -85,13 +85,19 @@ clean-sources:
 # Traffic Generation #
 ######################
 
+TRAFFIC_GEN ?= util/gen_jobs.py
+TRAFFIC_TB ?= dma_mesh
+TRAFFIC_TYPE ?= random
+TRAFFIC_RW ?= read
+TRAFFIC_OUTDIR ?= test/jobs
+
 .PHONY: jobs clean-jobs
-jobs: util/gen_jobs.py
-	mkdir -p test/jobs
-	./util/gen_jobs.py --out_dir test/jobs
+jobs: $(TRAFFIC_GEN)
+	mkdir -p $(TRAFFIC_OUTDIR)
+	$(TRAFFIC_GEN) --out_dir $(TRAFFIC_OUTDIR) --tb $(TRAFFIC_TB) --type $(TRAFFIC_TYPE) --rw $(TRAFFIC_RW)
 
 clean-jobs:
-	rm -rf test/jobs
+	rm -rf $(TRAFFIC_OUTDIR)
 
 ########################
 # QuestaSim Simulation #

src/floo_axi_chimney.sv

@@ -40,8 +40,8 @@ module floo_axi_chimney
   parameter rob_type_e RoBType              = NoRoB,
   /// Capacity of the reorder buffer
   parameter int unsigned ReorderBufferSize  = 32,
-  /// Only used for XYRouting
-  parameter type xy_id_t                    = logic,
+  /// Type of Coordinates/Id
+  parameter type id_t                       = logic,
   /// Cut timing paths of outgoing requests
   parameter bit CutAx                       = 1'b0,
   /// Cut timing paths of incoming responses
@@ -61,8 +61,7 @@ module floo_axi_chimney
   output axi_out_req_t axi_out_req_o,
   input  axi_out_rsp_t axi_out_rsp_i,
   /// Coordinates/ID of the current tile
-  input  xy_id_t  xy_id_i,
-  input  src_id_t id_i,
+  input  id_t  id_i,
   /// Output to NoC
   output floo_req_t floo_req_o,
   output floo_rsp_t floo_rsp_o,
@@ -120,8 +119,6 @@ module floo_axi_chimney
   typedef enum logic {SelAw, SelW} aw_w_sel_e;
   aw_w_sel_e aw_w_sel_q, aw_w_sel_d;
 
-  typedef dst_id_t id_t;
-
   // ID tracking
   typedef struct packed {
     axi_in_id_t id;
@@ -133,7 +130,6 @@ module floo_axi_chimney
 
   // Routing
   id_t [NumAxiChannels-1:0] dst_id;
-  id_t src_id;
 
   id_out_buf_t aw_out_data_in, aw_out_data_out;
   id_out_buf_t ar_out_data_in, ar_out_data_out;
@@ -357,12 +353,11 @@ module floo_axi_chimney
 
 
   if (RouteAlgo == XYRouting) begin : gen_xy_routing
-    xy_id_t aw_xy_id_q, aw_xy_id, ar_xy_id;
-    assign src_id = xy_id_i;
-    assign aw_xy_id.x = axi_aw_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)];
-    assign aw_xy_id.y = axi_aw_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)];
-    assign ar_xy_id.x = axi_ar_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)];
-    assign ar_xy_id.y = axi_ar_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)];
+    id_t aw_xy_id_q, aw_xy_id, ar_xy_id;
+    assign aw_xy_id.x = axi_aw_queue.addr[XYAddrOffsetX+:$bits(id_i.x)];
+    assign aw_xy_id.y = axi_aw_queue.addr[XYAddrOffsetY+:$bits(id_i.y)];
+    assign ar_xy_id.x = axi_ar_queue.addr[XYAddrOffsetX+:$bits(id_i.x)];
+    assign ar_xy_id.y = axi_ar_queue.addr[XYAddrOffsetY+:$bits(id_i.y)];
     assign dst_id[AxiAw] = aw_xy_id;
     assign dst_id[AxiAr] = ar_xy_id;
     assign dst_id[AxiW]  = aw_xy_id_q;
@@ -371,7 +366,6 @@ module floo_axi_chimney
     `FFL(aw_xy_id_q, aw_xy_id, axi_aw_queue_valid_out && axi_aw_queue_ready_in, '0)
   end else if (RouteAlgo == IdTable) begin : gen_id_table_routing
     id_t aw_id_q, aw_id, ar_id;
-    assign src_id = id_i;
     assign aw_id = axi_aw_queue.addr[IdTableAddrOffset+:$bits(id_i)];
     assign ar_id = axi_ar_queue.addr[IdTableAddrOffset+:$bits(id_i)];
     assign dst_id[AxiAw] = aw_id;
@@ -394,7 +388,7 @@ module floo_axi_chimney
     floo_axi_aw.hdr.rob_req = aw_rob_req_out;
     floo_axi_aw.hdr.rob_idx = aw_rob_idx_out;
     floo_axi_aw.hdr.dst_id  = dst_id[AxiAw];
-    floo_axi_aw.hdr.src_id  = src_id;
+    floo_axi_aw.hdr.src_id  = id_i;
     floo_axi_aw.hdr.last    = 1'b1;
     floo_axi_aw.hdr.axi_ch  = AxiAw;
     floo_axi_aw.hdr.atop    = axi_aw_queue.atop != axi_pkg::ATOP_NONE;
@@ -406,7 +400,7 @@ module floo_axi_chimney
     floo_axi_w.hdr.rob_req  = aw_rob_req_out;
     floo_axi_w.hdr.rob_idx  = aw_rob_idx_out;
     floo_axi_w.hdr.dst_id   = dst_id[AxiW];
-    floo_axi_w.hdr.src_id   = src_id;
+    floo_axi_w.hdr.src_id   = id_i;
     floo_axi_w.hdr.last     = axi_req_in.w.last;
     floo_axi_w.hdr.axi_ch   = AxiW;
     floo_axi_w.w            = axi_req_in.w;
@@ -417,7 +411,7 @@ module floo_axi_chimney
     floo_axi_ar.hdr.rob_req = ar_rob_req_out;
     floo_axi_ar.hdr.rob_idx = ar_rob_idx_out;
     floo_axi_ar.hdr.dst_id  = dst_id[AxiAr];
-    floo_axi_ar.hdr.src_id  = src_id;
+    floo_axi_ar.hdr.src_id  = id_i;
     floo_axi_ar.hdr.last    = 1'b1;
     floo_axi_ar.hdr.axi_ch  = AxiAr;
     floo_axi_ar.ar          = axi_ar_queue;
@@ -428,7 +422,7 @@ module floo_axi_chimney
     floo_axi_b.hdr.rob_req  = aw_out_data_out.rob_req;
     floo_axi_b.hdr.rob_idx  = aw_out_data_out.rob_idx;
     floo_axi_b.hdr.dst_id   = aw_out_data_out.src_id;
-    floo_axi_b.hdr.src_id   = src_id;
+    floo_axi_b.hdr.src_id   = id_i;
     floo_axi_b.hdr.last     = 1'b1;
     floo_axi_b.hdr.axi_ch   = AxiB;
     floo_axi_b.hdr.atop     = aw_out_data_out.atop;
@@ -441,7 +435,7 @@ module floo_axi_chimney
     floo_axi_r.hdr.rob_req  = ar_out_data_out.rob_req;
     floo_axi_r.hdr.rob_idx  = ar_out_data_out.rob_idx;
     floo_axi_r.hdr.dst_id   = ar_out_data_out.src_id;
-    floo_axi_r.hdr.src_id   = src_id;
+    floo_axi_r.hdr.src_id   = id_i;
     floo_axi_r.hdr.last     = axi_out_rsp_i.r.last;
     floo_axi_r.hdr.axi_ch   = AxiR;
     floo_axi_r.hdr.atop     = ar_out_data_out.atop;

src/floo_narrow_wide_chimney.sv

@@ -55,8 +55,7 @@ module floo_narrow_wide_chimney
   parameter bit CutAx                            = 1'b1,
   /// Cut timing paths of incoming responses from the NoC
   parameter bit CutRsp                           = 1'b1,
-  /// Only used for XYRouting
-  parameter type xy_id_t                         = logic,
+  /// Type of Coordinates/Id
   parameter type id_t                            = logic,
   /// Only used for IDRouting
   parameter type id_rule_t                       = logic,
@@ -79,7 +78,6 @@ module floo_narrow_wide_chimney
   output axi_wide_out_req_t axi_wide_out_req_o,
   input  axi_wide_out_rsp_t axi_wide_out_rsp_i,
   /// Coordinates/ID of the current tile
-  input  xy_id_t    xy_id_i,
   input  id_t       id_i,
   /// Routing table
   input  id_rule_t[NumRules-1:0]  id_map_i,
@@ -188,7 +186,6 @@ module floo_narrow_wide_chimney
 
   // Routing
   id_t [NumNarrowWideAxiChannels-1:0] dst_id;
-  id_t src_id;
 
   narrow_id_out_buf_t narrow_aw_out_data_in, narrow_aw_out_data_out;
   narrow_id_out_buf_t narrow_ar_out_data_in, narrow_ar_out_data_out;
@@ -611,17 +608,16 @@ module floo_narrow_wide_chimney
 
 
   if (RouteAlgo == XYRouting) begin : gen_xy_routing
-    xy_id_t narrow_aw_xy_id_q, narrow_aw_xy_id, narrow_ar_xy_id;
-    xy_id_t wide_aw_xy_id_q, wide_aw_xy_id, wide_ar_xy_id;
-    assign src_id = xy_id_i;
-    assign narrow_aw_xy_id.x = axi_narrow_aw_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)];
-    assign narrow_aw_xy_id.y = axi_narrow_aw_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)];
-    assign narrow_ar_xy_id.x = axi_narrow_ar_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)];
-    assign narrow_ar_xy_id.y = axi_narrow_ar_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)];
-    assign wide_aw_xy_id.x = axi_wide_aw_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)];
-    assign wide_aw_xy_id.y = axi_wide_aw_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)];
-    assign wide_ar_xy_id.x = axi_wide_ar_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)];
-    assign wide_ar_xy_id.y = axi_wide_ar_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)];
+    id_t narrow_aw_xy_id_q, narrow_aw_xy_id, narrow_ar_xy_id;
+    id_t wide_aw_xy_id_q, wide_aw_xy_id, wide_ar_xy_id;
+    assign narrow_aw_xy_id.x = axi_narrow_aw_queue.addr[XYAddrOffsetX+:$bits(id_i.x)];
+    assign narrow_aw_xy_id.y = axi_narrow_aw_queue.addr[XYAddrOffsetY+:$bits(id_i.y)];
+    assign narrow_ar_xy_id.x = axi_narrow_ar_queue.addr[XYAddrOffsetX+:$bits(id_i.x)];
+    assign narrow_ar_xy_id.y = axi_narrow_ar_queue.addr[XYAddrOffsetY+:$bits(id_i.y)];
+    assign wide_aw_xy_id.x = axi_wide_aw_queue.addr[XYAddrOffsetX+:$bits(id_i.x)];
+    assign wide_aw_xy_id.y = axi_wide_aw_queue.addr[XYAddrOffsetY+:$bits(id_i.y)];
+    assign wide_ar_xy_id.x = axi_wide_ar_queue.addr[XYAddrOffsetX+:$bits(id_i.x)];
+    assign wide_ar_xy_id.y = axi_wide_ar_queue.addr[XYAddrOffsetY+:$bits(id_i.y)];
     assign dst_id[NarrowAw] = narrow_aw_xy_id;
     assign dst_id[NarrowAr] = narrow_ar_xy_id;
     assign dst_id[NarrowW]  = narrow_aw_xy_id_q;
@@ -692,7 +688,7 @@ module floo_narrow_wide_chimney
     floo_narrow_aw.hdr.rob_req  = narrow_aw_rob_req_out;
     floo_narrow_aw.hdr.rob_idx  = rob_idx_t'(narrow_aw_rob_idx_out);
     floo_narrow_aw.hdr.dst_id   = dst_id[NarrowAw];
-    floo_narrow_aw.hdr.src_id   = src_id;
+    floo_narrow_aw.hdr.src_id   = id_i;
     floo_narrow_aw.hdr.last     = 1'b1;
     floo_narrow_aw.hdr.axi_ch   = NarrowAw;
     floo_narrow_aw.hdr.atop     = axi_narrow_aw_queue.atop != axi_pkg::ATOP_NONE;
@@ -704,7 +700,7 @@ module floo_narrow_wide_chimney
     floo_narrow_w.hdr.rob_req   = narrow_aw_rob_req_out;
     floo_narrow_w.hdr.rob_idx   = rob_idx_t'(narrow_aw_rob_idx_out);
     floo_narrow_w.hdr.dst_id    = dst_id[NarrowW];
-    floo_narrow_w.hdr.src_id    = src_id;
+    floo_narrow_w.hdr.src_id    = id_i;
     floo_narrow_w.hdr.last      = axi_narrow_req_in.w.last;
     floo_narrow_w.hdr.axi_ch    = NarrowW;
     floo_narrow_w.w             = axi_narrow_req_in.w;
@@ -715,7 +711,7 @@ module floo_narrow_wide_chimney
     floo_narrow_ar.hdr.rob_req  = narrow_ar_rob_req_out;
     floo_narrow_ar.hdr.rob_idx  = rob_idx_t'(narrow_ar_rob_idx_out);
     floo_narrow_ar.hdr.dst_id   = dst_id[NarrowAr];
-    floo_narrow_ar.hdr.src_id   = src_id;
+    floo_narrow_ar.hdr.src_id   = id_i;
     floo_narrow_ar.hdr.last     = 1'b1;
     floo_narrow_ar.hdr.axi_ch   = NarrowAr;
     floo_narrow_ar.ar           = axi_narrow_ar_queue;
@@ -726,7 +722,7 @@ module floo_narrow_wide_chimney
     floo_narrow_b.hdr.rob_req = narrow_aw_out_data_out.rob_req;
     floo_narrow_b.hdr.rob_idx = rob_idx_t'(narrow_aw_out_data_out.rob_idx);
     floo_narrow_b.hdr.dst_id  = narrow_aw_out_data_out.src_id;
-    floo_narrow_b.hdr.src_id  = src_id;
+    floo_narrow_b.hdr.src_id  = id_i;
     floo_narrow_b.hdr.last    = 1'b1;
     floo_narrow_b.hdr.axi_ch  = NarrowB;
     floo_narrow_b.hdr.atop    = narrow_aw_out_data_out.atop;
@@ -739,7 +735,7 @@ module floo_narrow_wide_chimney
     floo_narrow_r.hdr.rob_req = narrow_ar_out_data_out.rob_req;
     floo_narrow_r.hdr.rob_idx = rob_idx_t'(narrow_ar_out_data_out.rob_idx);
     floo_narrow_r.hdr.dst_id  = narrow_ar_out_data_out.src_id;
-    floo_narrow_r.hdr.src_id  = src_id;
+    floo_narrow_r.hdr.src_id  = id_i;
     floo_narrow_r.hdr.axi_ch  = NarrowR;
     floo_narrow_r.hdr.last    = axi_narrow_out_rsp_i.r.last;
     floo_narrow_r.hdr.atop    = narrow_ar_out_data_out.atop;
@@ -752,7 +748,7 @@ module floo_narrow_wide_chimney
     floo_wide_aw.hdr.rob_req  = wide_aw_rob_req_out;
     floo_wide_aw.hdr.rob_idx  = rob_idx_t'(wide_aw_rob_idx_out);
     floo_wide_aw.hdr.dst_id   = dst_id[WideAw];
-    floo_wide_aw.hdr.src_id   = src_id;
+    floo_wide_aw.hdr.src_id   = id_i;
     floo_wide_aw.hdr.last     = 1'b1;
     floo_wide_aw.hdr.axi_ch   = WideAw;
     floo_wide_aw.aw           = axi_wide_aw_queue;
@@ -763,7 +759,7 @@ module floo_narrow_wide_chimney
     floo_wide_w.hdr.rob_req = wide_aw_rob_req_out;
     floo_wide_w.hdr.rob_idx = rob_idx_t'(wide_aw_rob_idx_out);
     floo_wide_w.hdr.dst_id  = dst_id[WideW];
-    floo_wide_w.hdr.src_id  = src_id;
+    floo_wide_w.hdr.src_id  = id_i;
     floo_wide_w.hdr.last    = axi_wide_req_in.w.last;
     floo_wide_w.hdr.axi_ch  = WideW;
     floo_wide_w.w           = axi_wide_req_in.w;
@@ -774,7 +770,7 @@ module floo_narrow_wide_chimney
     floo_wide_ar.hdr.rob_req  = wide_ar_rob_req_out;
     floo_wide_ar.hdr.rob_idx  = rob_idx_t'(wide_ar_rob_idx_out);
     floo_wide_ar.hdr.dst_id   = dst_id[WideAr];
-    floo_wide_ar.hdr.src_id   = src_id;
+    floo_wide_ar.hdr.src_id   = id_i;
     floo_wide_ar.hdr.last     = 1'b1;
     floo_wide_ar.hdr.axi_ch   = WideAr;
     floo_wide_ar.ar           = axi_wide_ar_queue;
@@ -785,7 +781,7 @@ module floo_narrow_wide_chimney
     floo_wide_b.hdr.rob_req = wide_aw_out_data_out.rob_req;
     floo_wide_b.hdr.rob_idx = rob_idx_t'(wide_aw_out_data_out.rob_idx);
     floo_wide_b.hdr.dst_id  = wide_aw_out_data_out.src_id;
-    floo_wide_b.hdr.src_id  = src_id;
+    floo_wide_b.hdr.src_id  = id_i;
     floo_wide_b.hdr.last    = 1'b1;
     floo_wide_b.hdr.axi_ch  = WideB;
     floo_wide_b.b           = axi_wide_meta_buf_rsp_out.b;
@@ -797,7 +793,7 @@ module floo_narrow_wide_chimney
     floo_wide_r.hdr.rob_req = wide_ar_out_data_out.rob_req;
     floo_wide_r.hdr.rob_idx = rob_idx_t'(wide_ar_out_data_out.rob_idx);
     floo_wide_r.hdr.dst_id  = wide_ar_out_data_out.src_id;
-    floo_wide_r.hdr.src_id  = src_id;
+    floo_wide_r.hdr.src_id  = id_i;
     floo_wide_r.hdr.axi_ch  = WideR;
     floo_wide_r.hdr.last    = axi_wide_out_rsp_i.r.last;
     floo_wide_r.r           = axi_wide_meta_buf_rsp_out.r;

src/floo_narrow_wide_router.sv

@@ -15,6 +15,7 @@ module floo_narrow_wide_router
     parameter int unsigned ChannelFifoDepth = 0,
     parameter int unsigned OutputFifoDepth  = 0,
     parameter route_algo_e RouteAlgo        = XYRouting,
+    parameter bit          XYRouteOpt       = 1'b1,
     /// Used for ID-based and XY routing
     parameter int unsigned IdWidth          = 0,
     parameter type         id_t             = logic[IdWidth-1:0],
@@ -85,6 +86,7 @@ module floo_narrow_wide_router
     .ChannelFifoDepth ( ChannelFifoDepth        ),
     .OutputFifoDepth  ( OutputFifoDepth         ),
     .RouteAlgo        ( RouteAlgo               ),
+    .XYRouteOpt       ( XYRouteOpt              ),
     .IdWidth          ( IdWidth                 ),
     .id_t             ( id_t                    ),
     .NumAddrRules     ( NumAddrRules            ),
@@ -112,6 +114,7 @@ module floo_narrow_wide_router
     .ChannelFifoDepth ( ChannelFifoDepth        ),
     .OutputFifoDepth  ( OutputFifoDepth         ),
     .RouteAlgo        ( RouteAlgo               ),
+    .XYRouteOpt       ( XYRouteOpt              ),
     .IdWidth          ( IdWidth                 ),
     .flit_t           ( floo_rsp_generic_flit_t ),
     .id_t             ( id_t                    ),
@@ -140,6 +143,7 @@ module floo_narrow_wide_router
     .ChannelFifoDepth ( ChannelFifoDepth          ),
     .OutputFifoDepth  ( OutputFifoDepth           ),
     .RouteAlgo        ( RouteAlgo                 ),
+    .XYRouteOpt       ( XYRouteOpt                ),
     .IdWidth          ( IdWidth                   ),
     .id_t             ( id_t                      ),
     .NumAddrRules     ( NumAddrRules              ),

src/floo_rob_wrapper.sv

@@ -130,13 +130,14 @@ module floo_rob_wrapper
     localparam int unsigned CounterWidth = $clog2(MaxRoTxnsPerId);
 
     logic push, pop;
+    logic counter_full;
     logic in_flight;
     dest_t prev_dest;
 
     // A new transaction can be pushed if it is the first one
     // i.e. `in_flight` is not set or if the previous transaction
     // has the same destination
-    assign push = ax_valid_i && (!in_flight || ax_dest_i == prev_dest);
+    assign push = ax_valid_i && (!in_flight || ax_dest_i == prev_dest) && !counter_full;
     // Whenever a response arrives we can pop the transaction
     assign pop = rsp_valid_i && rsp_last_i;
 
@@ -161,7 +162,7 @@ module floo_rob_wrapper
       .lookup_axi_id_i              ( ax_id_i             ),
       .lookup_mst_select_o          ( prev_dest           ),
       .lookup_mst_select_occupied_o ( in_flight           ),
-      .full_o                       ( /* TODO */          ),
+      .full_o                       ( counter_full        ),
       .push_axi_id_i                ( ax_id_i             ),
       .push_mst_select_i            ( ax_dest_i           ),
       .push_i                       ( push && ax_ready_i  ),  // Only push on handshake

src/floo_router.sv

@@ -24,6 +24,7 @@ module floo_router import floo_pkg::*; #(
   /// Configuration parameters for special network topologies
   parameter int unsigned NumInput         = NumRoutes,
   parameter int unsigned NumOutput        = NumRoutes,
+  parameter bit          XYRouteOpt       = 1'b1,
   parameter bit          NoLoopback       = 1'b1
 ) (
   input  logic                                       clk_i,
@@ -121,7 +122,7 @@ module floo_router import floo_pkg::*; #(
         if (in_route == out_route && NoLoopback) begin : gen_inout_identical
           assign masked_all_ready[in_route][v_chan][out_route] = '0;
           // TODO MICHAERO: assert no loopback routing!!!
-        end else if ((RouteAlgo == XYRouting) &&
+        end else if ((RouteAlgo == XYRouting) && XYRouteOpt &&
                     (in_route == South || in_route == North) &&
                     (out_route == East || out_route == West)) begin : gen_xy_opt
           assign masked_all_ready[in_route][v_chan][out_route] = '0;

test/floo_axi_rand_slave.sv

@@ -23,7 +23,7 @@ module floo_axi_rand_slave
   parameter time ApplTime = 2ns,
   parameter time TestTime = 8ns,
   parameter logic[AxiAddrWidth-1:0] DstStartAddr = '0,
-  parameter logic[AxiAddrWidth-1:0] DstEndAddr = '0,
+  parameter logic[AxiAddrWidth-1:0] DstEndAddr = '1,
   parameter slave_type_e SlaveType = MixedSlave,
   parameter int unsigned NumSlaves = 4,
   localparam logic[AxiAddrWidth-1:0] SlvAddrSpace = (DstEndAddr - DstStartAddr) / NumSlaves