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nw_router: Change interface again
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fischeti committed Sep 12, 2023
1 parent 8aefd37 commit 914c54b
Showing 1 changed file with 59 additions and 30 deletions.
89 changes: 59 additions & 30 deletions src/floo_narrow_wide_router.sv
Original file line number Diff line number Diff line change
Expand Up @@ -29,26 +29,55 @@ module floo_narrow_wide_router
input id_t xy_id_i,
input addr_rule_t [NumAddrRules-1:0] id_route_map_i,

input logic [NumInputs-1:0] floo_req_valid_i,
output logic [NumInputs-1:0] floo_req_ready_o,
input floo_req_t [NumInputs-1:0] floo_req_i,
input logic [NumOutputs-1:0] floo_rsp_valid_i,
output logic [NumOutputs-1:0] floo_rsp_ready_o,
input floo_rsp_t [NumOutputs-1:0] floo_rsp_i,
output logic [NumOutputs-1:0] floo_req_valid_o,
input logic [NumOutputs-1:0] floo_req_ready_i,
output floo_req_t [NumOutputs-1:0] floo_req_o,
output logic [NumInputs-1:0] floo_rsp_valid_o,
input logic [NumInputs-1:0] floo_rsp_ready_i,
output floo_rsp_t [NumInputs-1:0] floo_rsp_o,
input logic [NumRoutes-1:0] floo_wide_valid_i,
output logic [NumRoutes-1:0] floo_wide_ready_o,
input floo_wide_t [NumRoutes-1:0] floo_wide_i,
output logic [NumRoutes-1:0] floo_wide_valid_o,
input logic [NumRoutes-1:0] floo_wide_ready_i,
output floo_wide_t [NumRoutes-1:0] floo_wide_o
);

floo_req_chan_t [NumInputs-1:0] req_in, req_out;
floo_rsp_chan_t [NumOutputs-1:0] rsp_in, rsp_out;
floo_wide_chan_t [NumRoutes-1:0] wide_in, wide_out;
logic [NumInputs-1:0] req_valid_in, req_ready_out;
logic [NumInputs-1:0] rsp_valid_out, rsp_ready_in;
logic [NumOutputs-1:0] req_valid_out, req_ready_in;
logic [NumOutputs-1:0] rsp_valid_in, rsp_ready_out;
logic [NumRoutes-1:0] wide_valid_in, wide_valid_out;
logic [NumRoutes-1:0] wide_ready_in, wide_ready_out;

for (genvar i = 0; i < NumInputs; i++) begin : gen_chimney_req
assign req_in[i] = floo_req_i[i].req;
assign floo_req_o[i].req = req_out[i];
assign req_valid_in[i] = floo_req_i[i].valid;
assign rsp_ready_in[i] = floo_rsp_i[i].ready;
assign floo_rsp_o[i].valid = rsp_valid_out[i];
assign floo_req_o[i].ready = req_ready_out[i];
end

for (genvar i = 0; i < NumOutputs; i++) begin : gen_chimney_rsp
assign rsp_in[i] = floo_rsp_i[i].rsp;
assign floo_rsp_o[i].rsp = rsp_out[i];
assign rsp_valid_in[i] = floo_rsp_i[i].valid;
assign req_ready_in[i] = floo_req_i[i].ready;
assign floo_req_o[i].valid = req_valid_out[i];
assign floo_rsp_o[i].ready = rsp_ready_out[i];
assign wide_valid_in[i] = floo_wide_i[i].valid;
assign wide_ready_in[i] = floo_wide_i[i].ready;
assign floo_wide_o[i].valid = wide_valid_out[i];
assign floo_wide_o[i].ready = wide_ready_out[i];
end

for (genvar i = 0; i < NumRoutes; i++) begin : gen_chimney_wide
assign wide_in[i] = floo_wide_i[i].wide;
assign floo_wide_o[i].wide = wide_out[i];
assign wide_valid_in[i] = floo_wide_i[i].valid;
assign wide_ready_in[i] = floo_wide_i[i].ready;
assign floo_wide_o[i].valid = wide_valid_out[i];
assign floo_wide_o[i].ready = wide_ready_out[i];
end

floo_router #(
.NumPhysChannels ( 1 ),
.NumVirtChannels ( 1 ),
Expand All @@ -67,12 +96,12 @@ module floo_narrow_wide_router
.test_enable_i,
.xy_id_i,
.id_route_map_i,
.valid_i ( floo_req_valid_i ),
.ready_o ( floo_req_ready_o ),
.data_i ( floo_req_i ),
.valid_o ( floo_req_valid_o ),
.ready_i ( floo_req_ready_i ),
.data_o ( floo_req_o )
.valid_i ( req_valid_in ),
.ready_o ( req_ready_out ),
.data_i ( req_in ),
.valid_o ( req_valid_out ),
.ready_i ( req_ready_in ),
.data_o ( req_out )
);


Expand All @@ -94,12 +123,12 @@ module floo_narrow_wide_router
.test_enable_i,
.xy_id_i,
.id_route_map_i,
.valid_i ( floo_rsp_valid_i ),
.ready_o ( floo_rsp_ready_o ),
.data_i ( floo_rsp_i ),
.valid_o ( floo_rsp_valid_o ),
.ready_i ( floo_rsp_ready_i ),
.data_o ( floo_rsp_o )
.valid_i ( rsp_valid_in ),
.ready_o ( rsp_ready_out ),
.data_i ( rsp_in ),
.valid_o ( rsp_valid_out ),
.ready_i ( rsp_ready_in ),
.data_o ( rsp_out )
);


Expand All @@ -120,12 +149,12 @@ module floo_narrow_wide_router
.test_enable_i,
.xy_id_i,
.id_route_map_i,
.valid_i ( floo_wide_valid_i ),
.ready_o ( floo_wide_ready_o ),
.data_i ( floo_wide_i ),
.valid_o ( floo_wide_valid_o ),
.ready_i ( floo_wide_ready_i ),
.data_o ( floo_wide_o )
.valid_i ( wide_valid_in ),
.ready_o ( wide_ready_out ),
.data_i ( wide_in ),
.valid_o ( wide_valid_out ),
.ready_i ( wide_ready_in ),
.data_o ( wide_out )
);

endmodule

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