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chimney: Unify id_t parametrization
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@fischeti
fischeti committed Nov 10, 2023
1 parent 1c582c4 commit 83e01e2
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Showing 2 changed files with 34 additions and 44 deletions.
32 changes: 13 additions & 19 deletions src/floo_axi_chimney.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -40,8 +40,8 @@ module floo_axi_chimney
parameter rob_type_e RoBType = NoRoB,
/// Capacity of the reorder buffer
parameter int unsigned ReorderBufferSize = 32,
/// Only used for XYRouting
parameter type xy_id_t = logic,
/// Type of Coordinates/Id
parameter type id_t = logic,
/// Cut timing paths of outgoing requests
parameter bit CutAx = 1'b0,
/// Cut timing paths of incoming responses
Expand All @@ -61,8 +61,7 @@ module floo_axi_chimney
output axi_out_req_t axi_out_req_o,
input axi_out_rsp_t axi_out_rsp_i,
/// Coordinates/ID of the current tile
input xy_id_t xy_id_i,
input src_id_t id_i,
input id_t id_i,
/// Output to NoC
output floo_req_t floo_req_o,
output floo_rsp_t floo_rsp_o,
Expand Down Expand Up @@ -120,8 +119,6 @@ module floo_axi_chimney
typedef enum logic {SelAw, SelW} aw_w_sel_e;
aw_w_sel_e aw_w_sel_q, aw_w_sel_d;

typedef dst_id_t id_t;

// ID tracking
typedef struct packed {
axi_in_id_t id;
Expand All @@ -133,7 +130,6 @@ module floo_axi_chimney

// Routing
id_t [NumAxiChannels-1:0] dst_id;
id_t src_id;

id_out_buf_t aw_out_data_in, aw_out_data_out;
id_out_buf_t ar_out_data_in, ar_out_data_out;
Expand Down Expand Up @@ -357,12 +353,11 @@ module floo_axi_chimney


if (RouteAlgo == XYRouting) begin : gen_xy_routing
xy_id_t aw_xy_id_q, aw_xy_id, ar_xy_id;
assign src_id = xy_id_i;
assign aw_xy_id.x = axi_aw_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)];
assign aw_xy_id.y = axi_aw_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)];
assign ar_xy_id.x = axi_ar_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)];
assign ar_xy_id.y = axi_ar_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)];
id_t aw_xy_id_q, aw_xy_id, ar_xy_id;
assign aw_xy_id.x = axi_aw_queue.addr[XYAddrOffsetX+:$bits(id_i.x)];
assign aw_xy_id.y = axi_aw_queue.addr[XYAddrOffsetY+:$bits(id_i.y)];
assign ar_xy_id.x = axi_ar_queue.addr[XYAddrOffsetX+:$bits(id_i.x)];
assign ar_xy_id.y = axi_ar_queue.addr[XYAddrOffsetY+:$bits(id_i.y)];
assign dst_id[AxiAw] = aw_xy_id;
assign dst_id[AxiAr] = ar_xy_id;
assign dst_id[AxiW] = aw_xy_id_q;
Expand All @@ -371,7 +366,6 @@ module floo_axi_chimney
`FFL(aw_xy_id_q, aw_xy_id, axi_aw_queue_valid_out && axi_aw_queue_ready_in, '0)
end else if (RouteAlgo == IdTable) begin : gen_id_table_routing
id_t aw_id_q, aw_id, ar_id;
assign src_id = id_i;
assign aw_id = axi_aw_queue.addr[IdTableAddrOffset+:$bits(id_i)];
assign ar_id = axi_ar_queue.addr[IdTableAddrOffset+:$bits(id_i)];
assign dst_id[AxiAw] = aw_id;
Expand All @@ -394,7 +388,7 @@ module floo_axi_chimney
floo_axi_aw.hdr.rob_req = aw_rob_req_out;
floo_axi_aw.hdr.rob_idx = aw_rob_idx_out;
floo_axi_aw.hdr.dst_id = dst_id[AxiAw];
floo_axi_aw.hdr.src_id = src_id;
floo_axi_aw.hdr.src_id = id_i;
floo_axi_aw.hdr.last = 1'b1;
floo_axi_aw.hdr.axi_ch = AxiAw;
floo_axi_aw.hdr.atop = axi_aw_queue.atop != axi_pkg::ATOP_NONE;
Expand All @@ -406,7 +400,7 @@ module floo_axi_chimney
floo_axi_w.hdr.rob_req = aw_rob_req_out;
floo_axi_w.hdr.rob_idx = aw_rob_idx_out;
floo_axi_w.hdr.dst_id = dst_id[AxiW];
floo_axi_w.hdr.src_id = src_id;
floo_axi_w.hdr.src_id = id_i;
floo_axi_w.hdr.last = axi_req_in.w.last;
floo_axi_w.hdr.axi_ch = AxiW;
floo_axi_w.w = axi_req_in.w;
Expand All @@ -417,7 +411,7 @@ module floo_axi_chimney
floo_axi_ar.hdr.rob_req = ar_rob_req_out;
floo_axi_ar.hdr.rob_idx = ar_rob_idx_out;
floo_axi_ar.hdr.dst_id = dst_id[AxiAr];
floo_axi_ar.hdr.src_id = src_id;
floo_axi_ar.hdr.src_id = id_i;
floo_axi_ar.hdr.last = 1'b1;
floo_axi_ar.hdr.axi_ch = AxiAr;
floo_axi_ar.ar = axi_ar_queue;
Expand All @@ -428,7 +422,7 @@ module floo_axi_chimney
floo_axi_b.hdr.rob_req = aw_out_data_out.rob_req;
floo_axi_b.hdr.rob_idx = aw_out_data_out.rob_idx;
floo_axi_b.hdr.dst_id = aw_out_data_out.src_id;
floo_axi_b.hdr.src_id = src_id;
floo_axi_b.hdr.src_id = id_i;
floo_axi_b.hdr.last = 1'b1;
floo_axi_b.hdr.axi_ch = AxiB;
floo_axi_b.hdr.atop = aw_out_data_out.atop;
Expand All @@ -441,7 +435,7 @@ module floo_axi_chimney
floo_axi_r.hdr.rob_req = ar_out_data_out.rob_req;
floo_axi_r.hdr.rob_idx = ar_out_data_out.rob_idx;
floo_axi_r.hdr.dst_id = ar_out_data_out.src_id;
floo_axi_r.hdr.src_id = src_id;
floo_axi_r.hdr.src_id = id_i;
floo_axi_r.hdr.last = axi_out_rsp_i.r.last;
floo_axi_r.hdr.axi_ch = AxiR;
floo_axi_r.hdr.atop = ar_out_data_out.atop;
Expand Down
46 changes: 21 additions & 25 deletions src/floo_narrow_wide_chimney.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -55,8 +55,7 @@ module floo_narrow_wide_chimney
parameter bit CutAx = 1'b1,
/// Cut timing paths of incoming responses from the NoC
parameter bit CutRsp = 1'b1,
/// Only used for XYRouting
parameter type xy_id_t = logic,
/// Type of Coordinates/Id
parameter type id_t = logic,
/// Only used for IDRouting
parameter type id_rule_t = logic,
Expand All @@ -79,7 +78,6 @@ module floo_narrow_wide_chimney
output axi_wide_out_req_t axi_wide_out_req_o,
input axi_wide_out_rsp_t axi_wide_out_rsp_i,
/// Coordinates/ID of the current tile
input xy_id_t xy_id_i,
input id_t id_i,
/// Routing table
input id_rule_t[NumRules-1:0] id_map_i,
Expand Down Expand Up @@ -188,7 +186,6 @@ module floo_narrow_wide_chimney

// Routing
id_t [NumNarrowWideAxiChannels-1:0] dst_id;
id_t src_id;

narrow_id_out_buf_t narrow_aw_out_data_in, narrow_aw_out_data_out;
narrow_id_out_buf_t narrow_ar_out_data_in, narrow_ar_out_data_out;
Expand Down Expand Up @@ -611,17 +608,16 @@ module floo_narrow_wide_chimney


if (RouteAlgo == XYRouting) begin : gen_xy_routing
xy_id_t narrow_aw_xy_id_q, narrow_aw_xy_id, narrow_ar_xy_id;
xy_id_t wide_aw_xy_id_q, wide_aw_xy_id, wide_ar_xy_id;
assign src_id = xy_id_i;
assign narrow_aw_xy_id.x = axi_narrow_aw_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)];
assign narrow_aw_xy_id.y = axi_narrow_aw_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)];
assign narrow_ar_xy_id.x = axi_narrow_ar_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)];
assign narrow_ar_xy_id.y = axi_narrow_ar_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)];
assign wide_aw_xy_id.x = axi_wide_aw_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)];
assign wide_aw_xy_id.y = axi_wide_aw_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)];
assign wide_ar_xy_id.x = axi_wide_ar_queue.addr[XYAddrOffsetX+:$bits(xy_id_i.x)];
assign wide_ar_xy_id.y = axi_wide_ar_queue.addr[XYAddrOffsetY+:$bits(xy_id_i.y)];
id_t narrow_aw_xy_id_q, narrow_aw_xy_id, narrow_ar_xy_id;
id_t wide_aw_xy_id_q, wide_aw_xy_id, wide_ar_xy_id;
assign narrow_aw_xy_id.x = axi_narrow_aw_queue.addr[XYAddrOffsetX+:$bits(id_i.x)];
assign narrow_aw_xy_id.y = axi_narrow_aw_queue.addr[XYAddrOffsetY+:$bits(id_i.y)];
assign narrow_ar_xy_id.x = axi_narrow_ar_queue.addr[XYAddrOffsetX+:$bits(id_i.x)];
assign narrow_ar_xy_id.y = axi_narrow_ar_queue.addr[XYAddrOffsetY+:$bits(id_i.y)];
assign wide_aw_xy_id.x = axi_wide_aw_queue.addr[XYAddrOffsetX+:$bits(id_i.x)];
assign wide_aw_xy_id.y = axi_wide_aw_queue.addr[XYAddrOffsetY+:$bits(id_i.y)];
assign wide_ar_xy_id.x = axi_wide_ar_queue.addr[XYAddrOffsetX+:$bits(id_i.x)];
assign wide_ar_xy_id.y = axi_wide_ar_queue.addr[XYAddrOffsetY+:$bits(id_i.y)];
assign dst_id[NarrowAw] = narrow_aw_xy_id;
assign dst_id[NarrowAr] = narrow_ar_xy_id;
assign dst_id[NarrowW] = narrow_aw_xy_id_q;
Expand Down Expand Up @@ -692,7 +688,7 @@ module floo_narrow_wide_chimney
floo_narrow_aw.hdr.rob_req = narrow_aw_rob_req_out;
floo_narrow_aw.hdr.rob_idx = rob_idx_t'(narrow_aw_rob_idx_out);
floo_narrow_aw.hdr.dst_id = dst_id[NarrowAw];
floo_narrow_aw.hdr.src_id = src_id;
floo_narrow_aw.hdr.src_id = id_i;
floo_narrow_aw.hdr.last = 1'b1;
floo_narrow_aw.hdr.axi_ch = NarrowAw;
floo_narrow_aw.hdr.atop = axi_narrow_aw_queue.atop != axi_pkg::ATOP_NONE;
Expand All @@ -704,7 +700,7 @@ module floo_narrow_wide_chimney
floo_narrow_w.hdr.rob_req = narrow_aw_rob_req_out;
floo_narrow_w.hdr.rob_idx = rob_idx_t'(narrow_aw_rob_idx_out);
floo_narrow_w.hdr.dst_id = dst_id[NarrowW];
floo_narrow_w.hdr.src_id = src_id;
floo_narrow_w.hdr.src_id = id_i;
floo_narrow_w.hdr.last = axi_narrow_req_in.w.last;
floo_narrow_w.hdr.axi_ch = NarrowW;
floo_narrow_w.w = axi_narrow_req_in.w;
Expand All @@ -715,7 +711,7 @@ module floo_narrow_wide_chimney
floo_narrow_ar.hdr.rob_req = narrow_ar_rob_req_out;
floo_narrow_ar.hdr.rob_idx = rob_idx_t'(narrow_ar_rob_idx_out);
floo_narrow_ar.hdr.dst_id = dst_id[NarrowAr];
floo_narrow_ar.hdr.src_id = src_id;
floo_narrow_ar.hdr.src_id = id_i;
floo_narrow_ar.hdr.last = 1'b1;
floo_narrow_ar.hdr.axi_ch = NarrowAr;
floo_narrow_ar.ar = axi_narrow_ar_queue;
Expand All @@ -726,7 +722,7 @@ module floo_narrow_wide_chimney
floo_narrow_b.hdr.rob_req = narrow_aw_out_data_out.rob_req;
floo_narrow_b.hdr.rob_idx = rob_idx_t'(narrow_aw_out_data_out.rob_idx);
floo_narrow_b.hdr.dst_id = narrow_aw_out_data_out.src_id;
floo_narrow_b.hdr.src_id = src_id;
floo_narrow_b.hdr.src_id = id_i;
floo_narrow_b.hdr.last = 1'b1;
floo_narrow_b.hdr.axi_ch = NarrowB;
floo_narrow_b.hdr.atop = narrow_aw_out_data_out.atop;
Expand All @@ -739,7 +735,7 @@ module floo_narrow_wide_chimney
floo_narrow_r.hdr.rob_req = narrow_ar_out_data_out.rob_req;
floo_narrow_r.hdr.rob_idx = rob_idx_t'(narrow_ar_out_data_out.rob_idx);
floo_narrow_r.hdr.dst_id = narrow_ar_out_data_out.src_id;
floo_narrow_r.hdr.src_id = src_id;
floo_narrow_r.hdr.src_id = id_i;
floo_narrow_r.hdr.axi_ch = NarrowR;
floo_narrow_r.hdr.last = axi_narrow_out_rsp_i.r.last;
floo_narrow_r.hdr.atop = narrow_ar_out_data_out.atop;
Expand All @@ -752,7 +748,7 @@ module floo_narrow_wide_chimney
floo_wide_aw.hdr.rob_req = wide_aw_rob_req_out;
floo_wide_aw.hdr.rob_idx = rob_idx_t'(wide_aw_rob_idx_out);
floo_wide_aw.hdr.dst_id = dst_id[WideAw];
floo_wide_aw.hdr.src_id = src_id;
floo_wide_aw.hdr.src_id = id_i;
floo_wide_aw.hdr.last = 1'b1;
floo_wide_aw.hdr.axi_ch = WideAw;
floo_wide_aw.aw = axi_wide_aw_queue;
Expand All @@ -763,7 +759,7 @@ module floo_narrow_wide_chimney
floo_wide_w.hdr.rob_req = wide_aw_rob_req_out;
floo_wide_w.hdr.rob_idx = rob_idx_t'(wide_aw_rob_idx_out);
floo_wide_w.hdr.dst_id = dst_id[WideW];
floo_wide_w.hdr.src_id = src_id;
floo_wide_w.hdr.src_id = id_i;
floo_wide_w.hdr.last = axi_wide_req_in.w.last;
floo_wide_w.hdr.axi_ch = WideW;
floo_wide_w.w = axi_wide_req_in.w;
Expand All @@ -774,7 +770,7 @@ module floo_narrow_wide_chimney
floo_wide_ar.hdr.rob_req = wide_ar_rob_req_out;
floo_wide_ar.hdr.rob_idx = rob_idx_t'(wide_ar_rob_idx_out);
floo_wide_ar.hdr.dst_id = dst_id[WideAr];
floo_wide_ar.hdr.src_id = src_id;
floo_wide_ar.hdr.src_id = id_i;
floo_wide_ar.hdr.last = 1'b1;
floo_wide_ar.hdr.axi_ch = WideAr;
floo_wide_ar.ar = axi_wide_ar_queue;
Expand All @@ -785,7 +781,7 @@ module floo_narrow_wide_chimney
floo_wide_b.hdr.rob_req = wide_aw_out_data_out.rob_req;
floo_wide_b.hdr.rob_idx = rob_idx_t'(wide_aw_out_data_out.rob_idx);
floo_wide_b.hdr.dst_id = wide_aw_out_data_out.src_id;
floo_wide_b.hdr.src_id = src_id;
floo_wide_b.hdr.src_id = id_i;
floo_wide_b.hdr.last = 1'b1;
floo_wide_b.hdr.axi_ch = WideB;
floo_wide_b.b = axi_wide_meta_buf_rsp_out.b;
Expand All @@ -797,7 +793,7 @@ module floo_narrow_wide_chimney
floo_wide_r.hdr.rob_req = wide_ar_out_data_out.rob_req;
floo_wide_r.hdr.rob_idx = rob_idx_t'(wide_ar_out_data_out.rob_idx);
floo_wide_r.hdr.dst_id = wide_ar_out_data_out.src_id;
floo_wide_r.hdr.src_id = src_id;
floo_wide_r.hdr.src_id = id_i;
floo_wide_r.hdr.axi_ch = WideR;
floo_wide_r.hdr.last = axi_wide_out_rsp_i.r.last;
floo_wide_r.r = axi_wide_meta_buf_rsp_out.r;
Expand Down

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