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test: Add Support for AddrWidth != 32
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fischeti committed Sep 15, 2023
1 parent a5e6649 commit 2fd400a
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Showing 2 changed files with 4 additions and 4 deletions.
4 changes: 2 additions & 2 deletions test/floo_axi_rand_slave.sv
Original file line number Diff line number Diff line change
Expand Up @@ -22,8 +22,8 @@ module floo_axi_rand_slave
// TB Parameters
parameter time ApplTime = 2ns,
parameter time TestTime = 8ns,
parameter int unsigned DstStartAddr = 0,
parameter int unsigned DstEndAddr = 0,
parameter logic[AxiAddrWidth-1:0] DstStartAddr = '0,
parameter logic[AxiAddrWidth-1:0] DstEndAddr = '0,
parameter slave_type_e SlaveType = MixedSlave,
localparam int unsigned NumSlaves = 4,
localparam int unsigned SlvAddrSpace = (DstEndAddr - DstStartAddr) / NumSlaves
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4 changes: 2 additions & 2 deletions test/floo_dma_test_node.sv
Original file line number Diff line number Diff line change
Expand Up @@ -29,8 +29,8 @@ module floo_dma_test_node #(
parameter type axi_out_rsp_t = axi_rsp_t,
parameter int unsigned TFLenWidth = 32,
parameter int unsigned MemSysDepth = 0,
parameter int unsigned MemBaseAddr = 32'h0,
parameter int unsigned MemSize = 32'h10000,
parameter logic [AddrWidth-1:0] MemBaseAddr = 32'h0,
parameter logic [AddrWidth-1:0] MemSize = 32'h10000,
parameter bit MaskInvalidData = 1,
parameter bit RAWCouplingAvail = 1,
parameter bit HardwareLegalizer = 1,
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