[WIP] Bus prototype #2174
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[WIP] Bus prototype #2174
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This was referenced Nov 29, 2024
georgwiese
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Cherry-picked from #2174 With this PR, we run all prover functions in parallel when solving for the witness in `VmProcessor`. Interestingly, this didn't require any changes to the order in which things are done: We already ran the functions independently and applied the combined updates. So, this is a classic map-reduce. I think this change always makes sense, but is especially useful for the prover functions we have to set bus accumulator values. For example, in our RISC-V machine, the main machine has ~30 bus interactions, with a fairly expensive prover function for each. When used on top of #2173 and #2175, this accelerates second-stage witness generation for the main machine from ~10s to ~6s for the example mentioned in #2173.
leonardoalt
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Cherry-picked from #2174 With this PR, we run all prover functions in parallel when solving for the witness in `VmProcessor`. Interestingly, this didn't require any changes to the order in which things are done: We already ran the functions independently and applied the combined updates. So, this is a classic map-reduce. I think this change always makes sense, but is especially useful for the prover functions we have to set bus accumulator values. For example, in our RISC-V machine, the main machine has ~30 bus interactions, with a fairly expensive prover function for each. When used on top of #2173 and #2175, this accelerates second-stage witness generation for the main machine from ~10s to ~6s for the example mentioned in #2173.
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Superseded by #2191 |
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