Skip to content
/ Verilog Public

Compilation of codes and mini projects in Verilog for the principles of Computer Architecture.

License

MIT license
0 stars 0 forks Branches Tags Activity
Star
Notifications You must be signed in to change notification settings

paollacq/Verilog

BranchesTags

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

4 Commits
LICENSE
LICENSE
 
 
README.md
README.md
 
 
comparator_4bit_behavioral.v
comparator_4bit_behavioral.v
 
 
comparator_4bit_dataflow.v
comparator_4bit_dataflow.v
 
 
comparator_4bit_dataflow2.v
comparator_4bit_dataflow2.v
 
 
d_flipflop_beh_ass_high.v
d_flipflop_beh_ass_high.v
 
 
d_flipflop_beh_ass_high_low.v
d_flipflop_beh_ass_high_low.v
 
 
d_flipflop_beh_ass_low.v
d_flipflop_beh_ass_low.v
 
 
d_flipflop_beh_syc_high.v
d_flipflop_beh_syc_high.v
 
 
d_flipflop_beh_syc_low.v
d_flipflop_beh_syc_low.v
 
 
d_flipflop_beh_syn_high_low.v
d_flipflop_beh_syn_high_low.v
 
 
d_flipflop_behavioral.v
d_flipflop_behavioral.v
 
 
d_latch_behavioral.v
d_latch_behavioral.v
 
 
d_latch_behavioral_async.v
d_latch_behavioral_async.v
 
 
d_latch_dataflow.v
d_latch_dataflow.v
 
 
decode_3x8.v
decode_3x8.v
 
 
decoder_dataflow.v
decoder_dataflow.v
 
 
demux_1x4.v
demux_1x4.v
 
 
encode_4x2.v
encode_4x2.v
 
 
encoder_behavioral_priority.v
encoder_behavioral_priority.v
 
 
encoder_dataflow.v
encoder_dataflow.v
 
 
enconder_behavioral.v
enconder_behavioral.v
 
 
fifo.v
fifo.v
 
 
freq_div_by3.v
freq_div_by3.v
 
 
full_adder_4bit_behavioral.v
full_adder_4bit_behavioral.v
 
 
full_adder_4bit_dataflow.v
full_adder_4bit_dataflow.v
 
 
full_adder_4bit_structural.v
full_adder_4bit_structural.v
 
 
full_adder_4bit_tb.v
full_adder_4bit_tb.v
 
 
full_adder_behavioral.v
full_adder_behavioral.v
 
 
full_adder_dataflow.v
full_adder_dataflow.v
 
 
full_adder_structural.v
full_adder_structural.v
 
 
full_adder_tb.v
full_adder_tb.v
 
 
jk_flipflop.v
jk_flipflop.v
 
 
logic_gate_model.v
logic_gate_model.v
 
 
mealy_ooo_seq.v
mealy_ooo_seq.v
 
 
moore_000_seq.v
moore_000_seq.v
 
 
moore_seq_dec.v
moore_seq_dec.v
 
 
multiplexer_behavioral.v
multiplexer_behavioral.v
 
 
multiplexer_behavioral4x1.v
multiplexer_behavioral4x1.v
 
 
multiplexer_dataflow.v
multiplexer_dataflow.v
 
 
multiplexer_dataflow1.v
multiplexer_dataflow1.v
 
 
multiplexer_dataflow2.v
multiplexer_dataflow2.v
 
 
multiplexer_dataflow3.v
multiplexer_dataflow3.v
 
 
multiplexer_structural.v
multiplexer_structural.v
 
 
mux_2x1.v
mux_2x1.v
 
 
shift_5bits_reg_lr.v
shift_5bits_reg_lr.v
 
 
shift_5bits_reg_uni.v
shift_5bits_reg_uni.v
 
 
shifter_8bit_behavioral.v
shifter_8bit_behavioral.v
 
 
sr_flipflop.v
sr_flipflop.v
 
 
sram_dport.v
sram_dport.v
 
 
sram_dport_true.v
sram_dport_true.v
 
 
sram_sport_regout.v
sram_sport_regout.v
 
 
sram_sport_syn.v
sram_sport_syn.v
 
 
t_flipflop.v
t_flipflop.v
 
 

Repository files navigation

Verilog

Compilation of codes and mini projects in Verilog for the principles of Computer Architecture.

About

Compilation of codes and mini projects in Verilog for the principles of Computer Architecture.

Resources

Readme

License

MIT license
Activity

Stars

0 stars

Watchers

1 watching

Forks

0 forks
Report repository

Releases

No releases published

Packages

No packages published

Languages