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Change RX sampling time to happen in the middle of the bit #1

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sd2k9
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@sd2k9 sd2k9 commented Jul 7, 2013

Hi,

I used your project as starting point for implementing an UART module. While investigating it I found that the RX sampling happens very early inside a bit, see the commited before.png
This isn't very robust and could cause troube with faulty data sampling.
Therefore I changed the code to sample in the middle of the bit, as you can see in after.png

The change is rather large because I detected the issue during my rework of reducing the logic usage for CPLD, by removing the double sampling clock generation counters.
And I also added "Optimize Here" Markers for later trials - please ignore them for now.

Just let me know if something is unclear.

You can find my testbench and project setup here in case you're interested:
https://github.com/sd2k9/hdl_uart_echo

sd2k9 added 2 commits June 30, 2013 18:55
* Sample the RX data bits in the MIDDLE of the bit to be more robust,
  Synchronise the sampling point to every start bit received

Also add "Optimize Here" Markers for later trials - ignore them for now

Original Resources for Example CoolRunner II Project:
    |Macrocells     |Product Terms    |Function Block   |Registers      |Pins          |
    |Used/Tot       |Used/Tot         |Inps Used/Tot    |Used/Tot       |Used/Tot      |
    |229/256 ( 89%) |458 /896  ( 51%) |472 /640  ( 74%) |178/256 ( 70%) |20 /118 ( 17%)|

Resources for this commit:
    |Macrocells     |Product Terms    |Function Block   |Registers      |Pins          |
    |Used/Tot       |Used/Tot         |Inps Used/Tot    |Used/Tot       |Used/Tot      |
    |164/256 ( 64%) |339 /896  ( 38%) |376 /640  ( 59%) |119/256 ( 46%) |20 /118 ( 17%)|
@mathieugouin
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Hi, I would like to know if your commit 8c0cc8e (date: Jan 14th, 2016) is the equivalent of merging this pull request? Thanks!!

@pabennett
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Yes I believe so. I revisited the project back in January to fix a few outstanding bugs, one of which was the bit alignment.

@mathieugouin
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I was asking because this pull request is still open. Thanks for the great project by the way!

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3 participants