Skip to content
Change the repository type filter

All

    Repositories list

    • SoCMake

      Public
      CMake based hardware build system
      CMake
      GNU Lesser General Public License v3.0
      28150Updated Dec 23, 2024Dec 23, 2024
    • Common SystemVerilog components
      SystemVerilog
      Other
      148000Updated Nov 25, 2024Nov 25, 2024
    • riscv-dbg

      Public
      RISC-V Debug Support for our PULP RISC-V Cores
      SystemVerilog
      Other
      78000Updated Nov 20, 2024Nov 20, 2024
    • SystemVerilog
      Other
      15000Updated Nov 15, 2024Nov 15, 2024
    • Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
      Python
      GNU General Public License v3.0
      44010Updated Nov 7, 2024Nov 7, 2024
    • Python
      GNU General Public License v3.0
      0010Updated Oct 30, 2024Oct 30, 2024
    • This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
      SystemVerilog
      Other
      168000Updated Oct 17, 2024Oct 17, 2024
    • Verilog parser, preprocessor, and related tools for the Verilog-Perl package
      Perl
      Artistic License 2.0
      34000Updated Sep 2, 2024Sep 2, 2024
    • Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
      SystemVerilog
      Other
      30000Updated Aug 29, 2024Aug 29, 2024
    • C++ 17 Hardware abstraction layer generator from systemrdl
      C++
      GNU General Public License v3.0
      5000Updated Jun 5, 2024Jun 5, 2024
    • GNU toolchain for RISC-V, including GCC
      C
      Other
      1.2k000Updated May 6, 2024May 6, 2024