Merge pull request #91 from pascalgouedo/dd_pgo

Updated CHANGELOG.md, README.md and docs/README.md

README.md

@@ -2,8 +2,8 @@
 
 Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats, written in SystemVerilog.
 
-Maintainer: Luca Bertaccini <[email protected]><br>
-Principal Author: Stefan Mach <[email protected]>
+Maintainers: Pasquale Davide Schiavone <[email protected]>, Pascal Gouedo <[email protected]><br>
+Authors: Stefan Mach <smach@iis.ee.ethz.ch>, Luca Bertaccini <lbertaccini@iis.ee.ethz.ch>
 
 ## Features
 

docs/CHANGELOG.md

@@ -8,7 +8,22 @@ In this sense, we interpret the "Public API" of a hardware module as its port/pa
 Versions of the IP in the same major relase are "pin-compatible" with each other. Minor relases are permitted to add new parameters as long as their default bindings ensure backwards compatibility.
 
 
-## [Unreleased]
+## [0.8.0] - 2023-06-02
+
+### Added
+- Add external reg enable to slices [(#89)](https://github.com/openhwgroup/cvfpu/pull/89)
+- Integrate new 32b divider [(#79)](https://github.com/openhwgroup/cvfpu/pull/79)
+
+### Changed
+- CHANGELOG.md, README.md and docs/README.md
+- Moved @lucabertaccini to Authors
+- Added Pasquale Davide Schiavone and Pascal Gouedo as maintainers
+
+### Fixed
+- multifmt slice uses wrong FP width for third operand [(#86)](https://github.com/openhwgroup/cvfpu/issues/86)
+- Fix DivSqrt lanes synchronization [(#90)](https://github.com/openhwgroup/cvfpu/pull/90)
+
+## [0.7.0] - 2023-03-20
 
 ### Added
 - Citation file `CITATION.cff`
@@ -18,10 +33,13 @@ Versions of the IP in the same major relase are "pin-compatible" with each other
 
 ### Changed
 - Code ownership to @lucabertaccini
+- Fix licence headers
 
 ### Fixed
 - Fix de-synchronization among vectorial lanes during variable-latency operations (`fdiv`, `fsqrt`)
-
+- Correct sign for RDN in floating point multiplications ([#54](https://github.com/openhwgroup/cvfpu/issues/54), [#63](https://github.com/openhwgroup/cvfpu/issues/63), [#728](https://github.com/openhwgroup/cv32e40p/issues/728))
+- Fix shift amount width in fma and fma_multi [(#66)](https://github.com/openhwgroup/cvfpu/pull/66)
+- Fix f2i cast edge cases [(#64)](https://github.com/openhwgroup/cvfpu/pull/64)
 
 ## [0.6.6] - 2021-04-19
 

docs/README.md

@@ -33,13 +33,14 @@ SystemVerilog `interface`s are not used due to poor support in some EDA tools.
 The configuration parameters use data types defined in `fpnew_pkg` which are structs containing multi-dimensional arrays of custom enumeration types.
 For more in-depth explanations on how to configure the unit and the layout of the types used, please refer to the [Configuration Section](#configuration).
 
-|  Parameter Name  |                                                         Description                                                          |
-|------------------|------------------------------------------------------------------------------------------------------------------------------|
-| `Features`       | Specifies the features of the FPU, such as the set of supported formats and operations.                                      |
-| `Implementation` | Allows to control how the above features are implemented, such as the number of pipeline stages and architecture of subunits |
-| `TagType`        | The SystemVerilog data type of the operation tag                                                                             |
-| `TrueSIMDClass`  | If enabled, the result of a classify operation in vectorial mode will be RISC-V compliant if each output has at least 10 bits|
-| `EnableSIMDMask` | Enable the RISC-V floating-point status flags masking of inactive vectorial lanes. When disabled, `simd_mask_i` is inactive  |
+|  Parameter Name  |                                                         Description                                                           |
+|------------------|-------------------------------------------------------------------------------------------------------------------------------|
+| `Features`       | Specifies the features of the FPU, such as the set of supported formats and operations.                                       |
+| `Implementation` | Allows to control how the above features are implemented, such as the number of pipeline stages and architecture of subunits  |
+| `PulpDivsqrt`    | Enables T-head-based DivSqrt unit when set to 0. Supported for FP32-only instances                                            |
+| `TagType`        | The SystemVerilog data type of the operation tag                                                                              |
+| `TrueSIMDClass`  | If enabled, the result of a classify operation in vectorial mode will be RISC-V compliant if each output has at least 10 bits |
+| `EnableSIMDMask` | Enable the RISC-V floating-point status flags masking of inactive vectorial lanes. When disabled, `simd_mask_i` is inactive   |
 
 ### Ports