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Altera flow support #2649

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Altera flow support #2649

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AngelaGonzalezMarino
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@AngelaGonzalezMarino AngelaGonzalezMarino commented Dec 4, 2024 •
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Integration of bitstream generation for Altera APU in general flow.
It follows #2647

  • Automatic generation of IPs and sources required for Altera FPGA
  • Adaptation of bootrom code (UART used in Altera is different and needs a different driver)
  • Generation of project for Quartus Pro adding required sources and constraints
  • Configuration file for openocd connection with vJTAG tap

AngelaGonzalezMarino and others added 25 commits November 27, 2024 13:07
@AngelaGonzalezMarino
altera IPs
fa7cd56
@AngelaGonzalezMarino
avalon axi conversion
1d462f5
@AngelaGonzalezMarino
vJTAG from Thales AVS
20cf845
@AngelaGonzalezMarino
APU design for altera
e6de252
@AngelaGonzalezMarino
pin mapping
87b04b3
@AngelaGonzalezMarino
constraints
5724455
@AngelaGonzalezMarino
add gpio submodule
1143019
@AngelaGonzalezMarino
integrate altera automatic flow in makefile
4f2ab09
@AngelaGonzalezMarino
integrate uart driver for altera
d8e7cca
@AngelaGonzalezMarino
add axi dw adapter
a6ed624
@AngelaGonzalezMarino
fix regfile complaint in quartus
26b1f13
@AngelaGonzalezMarino
add required settings for altera automation flow
b13349d
@AngelaGonzalezMarino
remove linux boot from bootrom code for altera for now
a11dc21
@AngelaGonzalezMarino
remove also sources list when cleaning
e0d9350
@AngelaGonzalezMarino
generate ips automatically
468ba53
@AngelaGonzalezMarino
Merge branch 'master' into altera_flow_support
bb9ee29
@AngelaGonzalezMarino
remove ip files that will be generated automatically
9e95080
@AngelaGonzalezMarino
generate ips from tcl
3b686a6
@AngelaGonzalezMarino
integrate ips generation in automatic flow and clean all generated files
f9a5345
@AngelaGonzalezMarino
flow generates ips outside of ip folder
923e27a
@AngelaGonzalezMarino
Merge branch 'openhwgroup:master' into altera_flow_support
59bb29d
@AngelaGonzalezMarino
remove intel interconnect files
b037655
@AngelaGonzalezMarino
automatically generate interconnect sources
bda3d9e
@AngelaGonzalezMarino
Merge branch 'altera_flow_support' of github.com:planvtech/cva6 into …
2ca787e 
…altera_flow_support
@AngelaGonzalezMarino
Merge branch 'openhwgroup:master' into altera_flow_support
63b183e
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❌ failed run, report available here.

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github-actions bot commented Dec 4, 2024

❌ failed run, report available here.

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github-actions bot commented Dec 5, 2024

❌ failed run, report available here.

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github-actions bot commented Dec 5, 2024

✔️ successful run, report available here.

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github-actions bot commented Dec 5, 2024

✔️ successful run, report available here.

@AngelaGonzalezMarino AngelaGonzalezMarino marked this pull request as ready for review December 5, 2024 15:58
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github-actions bot commented Dec 9, 2024

✔️ successful run, report available here.

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✔️ successful run, report available here.

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❌ failed run, report available here.

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❌ failed run, report available here.

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@JeanRochCoulon JeanRochCoulon Awaiting requested review from JeanRochCoulon JeanRochCoulon is a code owner

@zarubaf zarubaf Awaiting requested review from zarubaf zarubaf is a code owner

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