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fix size of vectors when AxiNumWords=1 #2639

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merged 6 commits into from
Dec 3, 2024
Merged

fix size of vectors when AxiNumWords=1 #2639

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1f0a8cc
fix size of vectors when AxiNumWords=1
AngelaGonzalezMarino Nov 28, 2024
372c140
Merge branch 'master' into fix_cache_line_width_64
AngelaGonzalezMarino Nov 29, 2024
e468791
Merge branch 'master' into fix_cache_line_width_64
AngelaGonzalezMarino Nov 29, 2024
5041d49
Merge branch 'master' into fix_cache_line_width_64
AngelaGonzalezMarino Dec 2, 2024
43c9c3f
use parameter to improve code readability
AngelaGonzalezMarino Dec 2, 2024
7d28ba9
Merge branch 'master' into fix_cache_line_width_64
AngelaGonzalezMarino Dec 2, 2024
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7 changes: 4 additions & 3 deletions core/cache_subsystem/wt_axi_adapter.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -64,6 +64,7 @@ module wt_axi_adapter
localparam MaxNumWords = $clog2(CVA6Cfg.AxiDataWidth / 8);
localparam AxiRdBlenIcache = CVA6Cfg.ICACHE_LINE_WIDTH / CVA6Cfg.AxiDataWidth - 1;
localparam AxiRdBlenDcache = CVA6Cfg.DCACHE_LINE_WIDTH / CVA6Cfg.AxiDataWidth - 1;
localparam AxiBlenWidth = AxiNumWords > 1 ? $clog2(AxiNumWords) : AxiNumWords;

///////////////////////////////////////////////////////
// request path
Expand All @@ -82,7 +83,7 @@ module wt_axi_adapter
logic axi_wr_valid, axi_rd_valid, axi_rd_rdy, axi_wr_rdy;
logic axi_rd_lock, axi_wr_lock, axi_rd_exokay, axi_wr_exokay, wr_exokay;
logic [CVA6Cfg.AxiAddrWidth-1:0] axi_rd_addr, axi_wr_addr;
logic [$clog2(AxiNumWords)-1:0] axi_rd_blen, axi_wr_blen;
logic [AxiBlenWidth-1:0] axi_rd_blen, axi_wr_blen;
logic [2:0] axi_rd_size, axi_wr_size;
logic [CVA6Cfg.AxiIdWidth-1:0]
axi_rd_id_in, axi_wr_id_in, axi_rd_id_out, axi_wr_id_out, wr_id_out;
Expand Down Expand Up @@ -170,14 +171,14 @@ module wt_axi_adapter
// If dcache_data.size MSB is set, we want to read as much as possible
axi_rd_size = dcache_data.size[2] ? MaxNumWords[2:0] : dcache_data.size;
if (dcache_data.size[2]) begin
axi_rd_blen = AxiRdBlenDcache[$clog2(AxiNumWords)-1:0];
axi_rd_blen = AxiRdBlenDcache[AxiBlenWidth-1:0];
end
end else begin
// Cast to AXI address width
axi_rd_addr = {{CVA6Cfg.AxiAddrWidth - CVA6Cfg.PLEN{1'b0}}, icache_data.paddr};
axi_rd_size = MaxNumWords[2:0]; // always request max number of words in case of ifill
if (!icache_data.nc) begin
axi_rd_blen = AxiRdBlenIcache[$clog2(AxiNumWords)-1:0];
axi_rd_blen = AxiRdBlenDcache[AxiBlenWidth-1:0];
end
end

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