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[Pmp] Verif plan TXT #2457

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2dcb741
make cv32a65x superscalar (#2348)
cathales Jul 10, 2024
48ef515
[Spike Yaml] Integrate Spike Yaml support. (#2304)
zchamski Jul 11, 2024
18bfc23
Change sh to bash in toolchain-builder README (#2355)
math-gout Jul 11, 2024
5fcc39d
remove round interval (#2353)
cathales Jul 11, 2024
8fa590b
CVXIF 1.0.0 (#2340)
Gchauvon Jul 12, 2024
3e62b0b
[Spike Yaml] HOTFIX: Add libyaml-cpp to preload list of RTL simulator…
zchamski Jul 12, 2024
e53c669
Enable tandem on smoke-gen tests in ci (#2357)
valentinThomazic Jul 12, 2024
da1c747
Increase simulation time on CSR tests (#2361)
AyoubJalali Jul 12, 2024
7165303
Doc lsu (#2359)
jzthales Jul 12, 2024
0cbd894
update port and config docs (#2363)
cathales Jul 12, 2024
c4b4216
Update cva6_requirements_specification.rst (#2364)
jquevremont Jul 12, 2024
8aa0f63
condition load and store modules (#2349)
Asmaa-Kassimi Jul 13, 2024
6c0e3f8
Verif: Add load hazard instructions (#2354)
AyoubJalali Jul 15, 2024
8c70976
docs: use correct commit for riscv-isa-manual submodule (#2368)
ASintzoff Jul 15, 2024
5f86058
[gen_from_riscv_config] fix access issues for PMP registers, improve …
AbdessamiiOukalrazqou Jul 21, 2024
95049c4
Bump verif/core-v-verif from `66cd091` to `20c2d30` (#2367)
dependabot[bot] Jul 22, 2024
8d413b7
doc PMA: cv32a65x is always idempotent and without caches (#2377)
JeanRochCoulon Jul 22, 2024
4a223be
decorrelate instr and addr depths in IQ (#2375)
cathales Jul 22, 2024
77c6cc3
fix CI regression testlists (#2378)
valentinThomazic Jul 22, 2024
aa4ced4
[gen_from_riscv_config] improve readme file and requirements file to …
AbdessamiiOukalrazqou Jul 22, 2024
4b2b6e2
Enable HPDcache in the UVM config (#2379)
AEzzejjari Jul 22, 2024
2acf5ba
fix ex_stage synthesis (#2384)
cathales Jul 23, 2024
d4809a7
change required dhrystone cycles count value (#2386)
valentinThomazic Jul 23, 2024
04ebfbd
Disable PMA execute and nonidempotent features (#2385)
JeanRochCoulon Jul 23, 2024
118f353
Exclude page fault exceptions if mmu isn't supported (#2387)
AyoubJalali Jul 23, 2024
7181278
Bump verif/core-v-verif from `20c2d30` to `f42effb` (#2381)
dependabot[bot] Jul 23, 2024
14be0af
solve simple lint errors (#2388)
Asmaa-Kassimi Jul 24, 2024
4ff16f9
set WtDcacheWbufDepth to 8 (#2390)
cathales Jul 24, 2024
846e1a1
[CI DEBUG] Track cause of failures in Spike version check. (#2360)
zchamski Jul 24, 2024
4c48a60
increase condition coverage in lsu, issue and commit stages (#2391)
Asmaa-Kassimi Jul 25, 2024
335c91c
[Xcelium flow] Xrun compile fixes (#2389)
CoralieAllioux Jul 25, 2024
3deb95a
cv64a6_mmu: add RISC-V ISA documentation to main page (#2393)
slgth Jul 25, 2024
1e48237
Update csr_regfile.sv to fix #2373 (#2374)
somyadashora Jul 25, 2024
631513e
Add RVU condition to increase coverage (#2396)
Asmaa-Kassimi Jul 25, 2024
fd489a1
Fix off by one error in PMP length (#2394)
Moschn Jul 25, 2024
e9648ea
Design documentation: AsciiDoc conversion (#2399)
slgth Jul 25, 2024
b438a8b
[gen_from_riscv_config] Improve the tool to support debug spec (#2398)
AbdessamiiOukalrazqou Jul 25, 2024
96b0508
[riscv-config] Update PMP definitions in cv32q65x spec (#2401)
zchamski Jul 25, 2024
211af02
Separate RAW and WAW process to fix CVXIF with Superscalar (#2395)
Gchauvon Jul 26, 2024
934823d
Add custom config in gitlab ci (#2405)
valentinThomazic Jul 26, 2024
a4583a6
[gen_from_riscv_config] improve readme file to support debug spec (#2…
AbdessamiiOukalrazqou Jul 26, 2024
2249202
docs: multiple fixes (#2409)
slgth Jul 26, 2024
6a649d6
docs: more fixes (#2412)
slgth Jul 26, 2024
8dcdf8f
[riscv-config] Add memory map entry to platform schema and to CV32A65…
zchamski Jul 26, 2024
bed9a17
Bump verif/core-v-verif from `1e7f049` to `bd42aee` (#2418)
dependabot[bot] Jul 30, 2024
4e9abb2
[cv32a65x] Remove unsupported Zifencei from riscv-config ISA string. …
zchamski Jul 30, 2024
d4b62d7
automate lint check process (#2414)
Asmaa-Kassimi Jul 30, 2024
6269f72
Bump verif/core-v-verif from `bd42aee` to `e06bd57` (#2422)
dependabot[bot] Jul 30, 2024
81671e3
Fixes and Update CVXIF non regression tests, regression and TB (#2424)
Gchauvon Aug 1, 2024
12be3ad
Solve some of W240 and W415a warnings increased by PMP entries (#2415)
Asmaa-Kassimi Aug 1, 2024
2e0a202
Add check CSR counter in UVM scoreboard (#2427)
AyoubJalali Aug 1, 2024
14fd617
Fix expected_synth.yml (#2428)
JeanRochCoulon Aug 2, 2024
ce4b25c
[HOT FIX] fix is_inside_execute (#2429)
JeanRochCoulon Aug 2, 2024
0c60bc6
Add debug_test to cva6 (#2339)
xiaoweish Aug 2, 2024
3059b1c
update riscv-isa-manual to riscv-isa-release-5ddbdd678-2024-08-01 (#2…
ASintzoff Aug 7, 2024
7435cb3
fix Spyglass job falsely reporting fail (#2435)
valentinThomazic Aug 7, 2024
4b51643
TANDEM Configuration fixes (#2420)
MarioOpenHWGroup Aug 9, 2024
af4e374
spyglass: remove useless assignments (#2439)
ASintzoff Aug 12, 2024
9b576c1
Configure uvm scoreboard to fix 64 issue (#2440)
AyoubJalali Aug 13, 2024
4f45b57
Add ariane_peripherals and testharness to fpga_filter (#2445)
Gchauvon Aug 13, 2024
e561897
spyglass: move assignments in if clause as only used there (#2444)
ASintzoff Aug 13, 2024
d2889fa
Display number of cycles at test termination (#2443)
JeanRochCoulon Aug 13, 2024
834e3e7
spyglass: ignore some multiple assignment W415a warnings (#2446)
ASintzoff Aug 14, 2024
89eb77a
[Spike tandem] Fix Yaml config files for CV32A65X. Fix Questa tandem.…
zchamski Aug 19, 2024
051ba34
spyglass: remove WRN_1024 warnings (#2448)
ASintzoff Aug 19, 2024
12f41b5
Bump verif/core-v-verif from `e06bd57` to `628ba12` (#2456)
dependabot[bot] Aug 20, 2024
76e5b40
fix single-step which was x in cv32a65x config and fix mcycle for dou…
cathales Aug 22, 2024
28affa2
[CI] use spike tandem on smoke-tests (#2438)
valentinThomazic Aug 22, 2024
37b5824
docs: expand wy-nav-content width to edge of screen (#2452)
EasyIP2023 Aug 22, 2024
4c36aaf
fix CI (#2460)
cathales Aug 23, 2024
064cec2
fix missing ZCMP condition in commit stage to increasse Code Coverage…
cathales Aug 24, 2024
339d3dd
Increase code coverage on second ALU by removing branch logic (#2362)
cathales Aug 26, 2024
53b51ac
do not use tandem on test suites in ci (#2463)
valentinThomazic Aug 26, 2024
faf4536
fix #2464: exception is not generated when INHIBIT CSR is accessed (#…
JeanRochCoulon Aug 27, 2024
0d2097b
Fix minstret (#2471)
cathales Aug 28, 2024
004f819
Tandem for 65x (#2473)
valentinThomazic Aug 28, 2024
6249bd1
[TANDEM] CSR Params Refactor + CSR API (#2407)
MarioOpenHWGroup Aug 28, 2024
776e013
[RVFI] Connect RVFI.intr to enable interrupts on TANDEM (#2475)
MarioOpenHWGroup Aug 29, 2024
668829d
Set the environment configuration only from env_cfg constraints. (#2408)
AEzzejjari Aug 29, 2024
a66efad
fix jal riscv-arch-test (#2479)
valentinThomazic Aug 30, 2024
111df66
fix hwconfig setup in cva6.py (#2484)
JeanRochCoulon Aug 30, 2024
8ef2859
Code clean-up of the number of register address bits (#2483)
JeanRochCoulon Aug 30, 2024
d577aaf
Fix vcs-uvm simulation flow (#2485)
AEzzejjari Aug 30, 2024
9362816
fix simulation errors not detected on ci w/ tandem (#2486)
valentinThomazic Aug 30, 2024
ea3a554
Bump core/cache_subsystem/hpdcache from `25ffa34` to `b4519e7` (#2466)
dependabot[bot] Aug 31, 2024
6561f2c
report_benchmark.py: fix Dhrystone cycles after PR #2484 (#2488)
ASintzoff Sep 2, 2024
e9382ba
Bump verif/core-v-verif csr-injection (#2491)
MarioOpenHWGroup Sep 4, 2024
6a4af75
UVM environment: mcountinhibit doesn't raise an exception (#2494)
AyoubJalali Sep 6, 2024
8070feb
spyglass: remove W528 warnings in decoder.sv (#2503)
ASintzoff Sep 19, 2024
f974e10
Add a basic mechanism for interrupt acknowledge. (#2502)
zchamski Sep 19, 2024
bc7eeb7
[interrupt verification] Add .uvmif support to global verif linker sc…
zchamski Sep 23, 2024
164d7c7
Add AW lock register to handle W FIFO push signal (#2461)
ricted98 Sep 24, 2024
923d9c2
Drive the AXI interface slave signals with 'Z in the active mode (#2511)
AEzzejjari Sep 24, 2024
967fc5d
Bump verif/core-v-verif from `c3d0c72` to `4e17969` (#2512)
dependabot[bot] Sep 24, 2024
860f47f
ci: Update phiwag/edatools gpg key (#2515)
niwis Sep 26, 2024
56532c6
Simplify CI (#2517)
JeanRochCoulon Sep 27, 2024
6ccd8d8
Refactor forwarding in issue_stage module (#2519)
jzthales Oct 1, 2024
c6ae849
put dhrystone in smoke job group and coremark in regress job group (#…
JeanRochCoulon Oct 1, 2024
ff01467
Fixed btb for FPGA targets (#2521)
FriedDede Oct 2, 2024
44072bf
[pmpcfg detailed spec] Add proposed CSR spec output. (#2522)
zchamski Oct 2, 2024
969c151
[PMP] Extracted PMP (#2476)
CoralieAllioux Oct 3, 2024
51653c6
Revert "[PMP] Extracted PMP (#2476)" (#2524)
JeanRochCoulon Oct 4, 2024
4a642d3
Resources and ecosystem (#2514)
jquevremont Oct 4, 2024
08c8165
Display report at the end of dhrystone and coremark executions (#2529)
JeanRochCoulon Oct 4, 2024
8f06d41
Update RESOURCES.md (#2530)
Oct 4, 2024
2ec2426
Add vcs-uvm-gate ISS target
JeanRochCoulon Oct 7, 2024
e7f4234
Set clock period at 20ns and fix vcs-uvm simulation time
JeanRochCoulon Oct 7, 2024
b744f9b
Create job dedicated to benchmark CVA6
JeanRochCoulon Oct 7, 2024
2b3a82f
Fix CVV#2531: Make mie.MSIE and mip.MSIP RO-zero, prevent SW writes t…
zchamski Oct 1, 2024
fea98c6
[HOTFIX] Fix Handling of CVXIF instruction being interrupted (#2537)
Gchauvon Oct 9, 2024
0649adc
Adding 10xE (#2533)
jquevremont Oct 9, 2024
5131fb0
doc PMP: rephrase PMP configuration description (#2540)
ASintzoff Oct 11, 2024
7ae870e
cv32a65x CI: Enlarge cache to increase bench result and switch from -…
JeanRochCoulon Oct 11, 2024
9c3aea2
Performance tb (#2543)
AnouarZajni Oct 11, 2024
c8f2c39
Use uvm testbench to run gate simulations (#2548)
JeanRochCoulon Oct 16, 2024
dff6271
Add an option to disable AXI assertions from the command line (#2545)
AEzzejjari Oct 16, 2024
1de0da8
always update prediction output based on RAM content (#2549)
AngelaGonzalezMarino Oct 16, 2024
7394941
Interrupt verif : Implement clear mechanism in interrupt's agent (#2527)
AyoubJalali Oct 16, 2024
be4a6ee
tristan_verification_specifications.adoc: 2023 version
ASintzoff Oct 10, 2024
a0f9dea
tristan: add 2024 work
ASintzoff Oct 10, 2024
48480c7
tristan doc: move files to sub-directory
ASintzoff Oct 16, 2024
cff48e4
Add tandem verification documentation (#2553)
zchamski Oct 17, 2024
0bf937a
increase code coverage in commit stage (#2555)
cathales Oct 18, 2024
67a6ae9
update riscv-isa-manual to riscv-isa-release-2c07aa2-2024-10-18 (#2560)
ASintzoff Oct 22, 2024
c1c2f9d
ci: print results in job logs (#2561)
cathales Oct 22, 2024
b4d000b
cv64a6_imafdch_sv39_wb_config: Fix undefined parameter (#2513)
niwis Oct 23, 2024
53472eb
Move timing statement outside of `always_comb` block (#2552)
ricted98 Oct 23, 2024
21dc824
Fix pmpaddr read logic considering G=2 (#2469)
Moschn Oct 23, 2024
20b64e8
Performance tb (#2562)
AnouarZajni Oct 23, 2024
0877e8e
Multicommits to shorten smoke-tests duration, to declare VLEN as para…
JeanRochCoulon Oct 23, 2024
45eaace
Revert "Multicommits to shorten smoke-tests duration, to declare VLEN…
JeanRochCoulon Oct 23, 2024
4ca7a3a
Fix: Replace riscv_pkg:VLEN by CVA6Cfg.VLEN
JeanRochCoulon Oct 17, 2024
8e605df
Declare VLEN as new CVA6 parameter
JeanRochCoulon Oct 17, 2024
1d0076e
smoke-hwconfig: run with vcs-uvm and use return0 test to speed-up CI …
JeanRochCoulon Oct 17, 2024
9cfadbe
Create dedicated linker scripts for cv32a65x configuration. When anot…
JeanRochCoulon Oct 17, 2024
37a9cf7
Create dedicated spike.yaml file for cv32a65x configuration. When ano…
JeanRochCoulon Oct 18, 2024
fd6037f
Set BHTEntries=128, cache=WT and scoreboardentries=8, Icache size=163…
JeanRochCoulon Oct 20, 2024
ce24338
Run 4 iterations of coremark to improve results
JeanRochCoulon Oct 20, 2024
8a45727
Split smoke-tests.sh into 3 tests to speed-up CI timing execution of …
JeanRochCoulon Oct 20, 2024
6fc8d60
Dhrystone_smoke.sh: smoke-smoke is done on dhrystone for the cv32a65x…
JeanRochCoulon Oct 20, 2024
9ceab19
Clean-up: Remove unused regression suites and tools from CI job scripts
JeanRochCoulon Oct 21, 2024
61c38ea
Install Verilator only if DV_SIMULATORS == veri-testharness
JeanRochCoulon Oct 21, 2024
01c636d
report_benchmarks.py: update results
JeanRochCoulon Oct 21, 2024
ab2283c
doc: keep documentation in sync with the code (#2558)
slgth Oct 25, 2024
9e670f6
acc_dispatcher: don't issue instruction from buffer if flushing (#2490)
mp-17 Nov 1, 2024
aeb0b64
cache_ctrl: Generalise AXI offset generation (#2573)
niwis Nov 4, 2024
7aad781
doc: pmp granularity equals to 8-byte (#2572)
ASintzoff Nov 4, 2024
0687510
document superscalar cv32a65x (frontend + decode) (#2570)
cathales Nov 4, 2024
9676d23
Mention that PR must be updated in CONTRIBUTING.md (#2568)
cathales Nov 4, 2024
51543db
fix readme links (#2575)
valentinThomazic Nov 4, 2024
3a9c2aa
[HOT FIX] Update expected gate count result (#2574)
JeanRochCoulon Nov 4, 2024
3d267f9
refactor gitlab ci & collect full fpga build artifacts (#2576)
valentinThomazic Nov 4, 2024
01845dd
Initialize `mock_uart` signals on reset (#2580)
ricted98 Nov 5, 2024
6bbc1e6
update the hpdcache to its latest version (#2579)
Nov 5, 2024
4604195
[benchmarks] Pass DV_OPTS to dhrystone execution. (#2582)
zchamski Nov 6, 2024
f2d88cd
RVV: :bug: fix exception propagation from Ara (#2583)
mp-17 Nov 6, 2024
a48fe03
New tutorial for coprocessor modification. (#2518)
joncapltd Nov 7, 2024
aea4e3d
Remove compile-time define from Makefile and update core-v-verif HASH…
AyoubJalali Nov 7, 2024
65285e5
Dev/hpdcache fpga (#2586)
Gchauvon Nov 7, 2024
4619a67
expand glob port maps (#2585)
cathales Nov 7, 2024
67f185c
Bump verif/core-v-verif from `72bd7ca` to `f73efc4` (#2593)
dependabot[bot] Nov 12, 2024
485c382
csr_regfile: Fix S-mode traps when H extension is enabled (#2587)
niwis Nov 12, 2024
5bc34d7
Revert "csr_regfile: Fix S-mode traps when H extension is enabled (#2…
JeanRochCoulon Nov 12, 2024
7ae45e1
use "testelf" branch for the gate simulation (#2595)
JeanRochCoulon Nov 12, 2024
4f5492d
Add failure checks in report_tandem script (#2597)
valentinThomazic Nov 12, 2024
16f37b9
Fix issue when NrPMPEntries=0 (#2589)
AngelaGonzalezMarino Nov 12, 2024
6a86ebd
add CVA6ConfigFpgaAltera parameter (#2590)
AngelaGonzalezMarino Nov 12, 2024
43edcd4
document issue stage (#2598)
cathales Nov 12, 2024
7eb59c3
iro: remove an unreachable statement (#2588)
cathales Nov 12, 2024
2d9936d
Disable superscalar for cv32a65x configuration (Enable single issue) …
JeanRochCoulon Nov 14, 2024
f54b9d4
csr_regfile: Fix S-mode traps when H extension is enabled (#2599)
niwis Nov 14, 2024
33c5d77
Altera opt 1 (#2592)
AngelaGonzalezMarino Nov 15, 2024
a283d3e
Define cv32a60x configuration (#2608)
JeanRochCoulon Nov 18, 2024
e7f27c1
Disable tandem on riscv-tests-v tests (#2609)
valentinThomazic Nov 18, 2024
2f81dba
Fixed wrong axi signal (#2614)
0BAB1 Nov 20, 2024
e571c1c
fix simu gate step 1: cva6.py refactor & collect report (#2621)
valentinThomazic Nov 20, 2024
6a8d1f4
Integrating the new version of the AXI agent (#2604)
AEzzejjari Nov 20, 2024
7ee22cd
Improving frontend documentation (#2617)
AEzzejjari Nov 20, 2024
25f2f31
Fix $fatal system task incorrect usage (#2619)
likeamahoney Nov 20, 2024
8a84f78
Increase Spike PMP granularity to 8. Update yaml spec files accordin…
zchamski Nov 21, 2024
c389382
Altera opt 2 (#2602)
AngelaGonzalezMarino Nov 21, 2024
7eb33df
Interrupt agent : Modify README also clean interrupt_pkg (#2571)
AyoubJalali Nov 21, 2024
f800707
docs: update URL in CSR access DV plan (fix #2625) (#2627)
ASintzoff Nov 22, 2024
2157aaa
Accelerate the performance of the AXI agent (#2631)
AEzzejjari Nov 25, 2024
5b1c194
UVM_ENV : Clean up CVA6 UVM env (#2633)
AyoubJalali Nov 26, 2024
6ee7a7d
CI fixes (#2634)
valentinThomazic Nov 27, 2024
7c326f5
Fix gate simulation: Update hpdcache_sram black box (#2632)
Gchauvon Nov 27, 2024
160c322
improve dashboard-provided log (#2636)
valentinThomazic Nov 28, 2024
dd649f2
Show config for smoke-bench job (#2637)
valentinThomazic Nov 28, 2024
b718824
Altera opt 3 (#2613)
AngelaGonzalezMarino Nov 28, 2024
820a8c6
Fix documentation build (#2641)
valentinThomazic Nov 29, 2024
aa62eec
Provide the correct environment for doc build (#2643)
valentinThomazic Nov 29, 2024
84e3a39
Bump verif/core-v-verif from `b7f57c1` to `9601c80` (#2642)
dependabot[bot] Nov 29, 2024
ba8ac71
use dcache_assoc_width (#2640)
AngelaGonzalezMarino Dec 2, 2024
9877af5
fix size of vectors when AxiNumWords=1 (#2639)
AngelaGonzalezMarino Dec 3, 2024
b5b316a
doc: fix build (cva6_frontend.adoc) (#2644)
ASintzoff Dec 3, 2024
23355d2
Pmp/extracted pmp master (#2528)
OlivierBetschi Dec 4, 2024
de0ebf0
add cv64a6_imafdch_sv39 config to cva6.py (#2646)
Cra2yPierr0t Dec 4, 2024
67648fb
draft verif plan for PMP
dat9val Jun 6, 2024
d0be54c
added PMP Verif Features and Verif Plan Draft
dat9val Jul 10, 2024
8ca4453
added priorities on some high-priority tests
dat9val Jul 12, 2024
8bed6e7
added priorities on some high-priority tests
dat9val Jul 12, 2024
5ccf779
Add PMP verif plan integrated in VP tool
OlivierBetschi Nov 7, 2024
c82d5ad
Add dvplan_PMP.md
OlivierBetschi Nov 7, 2024
273ac8c
Add PMP tests
OlivierBetschi Nov 7, 2024
3e953dc
Remove custom PMP test config
OlivierBetschi Nov 8, 2024
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Design documentation: AsciiDoc conversion (#2399)
  • Loading branch information
slgth authored Jul 25, 2024
commit e9648eaf8c3178ec671e89c4605dd89a66ff2ac2
496 changes: 496 additions & 0 deletions config/gen_from_riscv_config/cv32a65x/csr/csr.adoc

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232 changes: 232 additions & 0 deletions config/gen_from_riscv_config/cv32a65x/isa/isa.adoc

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185 changes: 185 additions & 0 deletions config/gen_from_riscv_config/scripts/libs/utils.py
Original file line number Diff line number Diff line change
@@ -539,6 +539,191 @@ def returnAsString(self):
r.table(header=_headers, data=reg_table)
return r.data

class AdocAddressBlock(AddressBlockClass):
"""Generates an AsciiDoc file from a IP-XACT register description"""

def __init__(self, name):
super().__init__("csr")
self.name = name
self.registerList = []
self.suffix = ".adoc"

def get_access_privilege(self, reg):
"""Registers with address bits [11:10] == 2'b11 are Read-Only
as per privileged ISA spec."""
# Handle register address ranges separated by dashes.
if (int(reg.address.split("-")[0], 0) & 0xC00) == 0xC00:
return "RO"
else:
return "RW"

def generate_label(self, name):
return "_" + name.replace('[','').replace(']','').upper()

def returnAsString(self):
registerlist = sorted(self.registerList, key=lambda reg: reg.address)
r = ""
regNameList = [reg.name.upper() for reg in registerlist]
regAddressList = [reg.address for reg in registerlist]
regPrivModeList = [reg.access for reg in registerlist]
regPrivAccessList = [self.get_access_privilege(reg) for reg in registerlist]
regDescrList = [reg.desc for reg in registerlist]
regRV32List = [reg.RV32 for reg in registerlist]
regRV64List = [reg.RV64 for reg in registerlist]

r += "////\n"
r += " Copyright (c) 2024 OpenHW Group\n"
r += " Copyright (c) 2024 Thales\n"
r += " SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1\n"
r += " Author: Abdessamii Oukalrazqou\n"
r += "////\n\n"

r += "=== %s\n\n"%self.name
r += "==== Conventions\n\n"

r += "In the subsequent sections, register fields are labeled with one of the following abbreviations:\n\n"

r += "* WPRI (Writes Preserve Values, Reads Ignore Values): read/write field reserved\n"
r += "for future use. For forward compatibility, implementations that do not\n"
r += "furnish these fields must make them read-only zero.\n"

r += "* WLRL (Write/Read Only Legal Values): read/write CSR field that specifies\n"
r += "behavior for only a subset of possible bit encodings, with other bit encodings\n"
r += "reserved.\n"

r += "* WARL (Write Any Values, Reads Legal Values): read/write CSR fields which are\n"
r += "only defined for a subset of bit encodings, but allow any value to be written\n"
r += "while guaranteeing to return a legal value whenever read.\n"

r += "* ROCST (Read-Only Constant): A special case of WARL field which admits only one\n"
r += "legal value, and therefore, behaves as a constant field that silently ignores\n"
r += "writes.\n"

r += "* ROVAR (Read-Only Variable): A special case of WARL field which can take\n"
r += "multiple legal values but cannot be modified by software and depends only on\n"
r += "the architectural state of the hart.\n\n"

r += "In particular, a register that is not internally divided\n"
r += "into multiple fields can be considered as containing a single field of XLEN bits.\n"
r += "This allows to clearly represent read-write registers holding a single legal value\n"
r += "(typically zero).\n\n"

r += "==== Register Summary\n\n"

r += "|===\n"
r += "|Address | Register Name | Privilege | Description\n\n"
for i, _ in enumerate(regNameList):
if regRV32List[i] | regRV64List[i]:
r += "|" + regAddressList[i] + \
f"| `<<{self.generate_label(regNameList[i])},{regNameList[i].upper()}>>`" + \
"|" + regPrivModeList[i] + regPrivAccessList[i] + \
"|" + str(regDescrList[i]) + "\n"
r += "|===\n\n"

r += "==== Register Description\n\n"
for reg in registerlist:
if reg.RV32 | reg.RV64:
r += "[[%s]]\n"%self.generate_label(reg.name)
r += "===== %s\n\n"%reg.name.upper()

r += "Address:: %s\n"%reg.address
if reg.resetValue:
# display the resetvalue in hex notation in the full length of the register
r += "Reset Value:: 0x%s\n"%f"{reg.resetValue[2:].zfill(int(reg.size/4))}"
# RO/RW privileges are encoded in register address.
r += "Privilege:: %s\n"%(reg.access + self.get_access_privilege(reg))
r += "Description:: %s\n\n"%(reg.desc)

reg_table = []
for field in reg.field:
if field.bitWidth == 1: # only one bit -> no range needed
bits = f"{field.bitlsb}"
else:
bits = f"[{field.bitmsb}:{field.bitlsb}]"
_line = [
bits,
field.name.upper(),
field.fieldreset,
field.fieldaccess,
(
Render.bitmask(field.andMask, field.orMask)
if field.andMask and field.orMask
else field.bitlegal
),
]
_line.append(field.fieldDesc)
reg_table.append(_line)

reg_table = sorted(
reg_table, key=lambda x: int(x[0].strip("[]").split(":")[0])
)
# table of the register
r += "|===\n"
r += "| Bits | Field Name | Reset Value | Type | Legal Values | Description\n\n"
for reg in reg_table:
for col in reg:
r +="| %s "%col.replace('\n','')
r += "\n"
r += "|===\n\n"

return r

class InstadocBlock(InstructionBlockClass):
"""Generates a ISA AsciiDoc file from RISC-V Config Yaml register description"""

def __init__(self, name):
super().__init__("isa")
self.name = name
self.Instructionlist = []
self.suffix = ".adoc"

def returnAsString(self):
r = ""
InstrNameList = [reg.key for reg in self.Instructionlist]
InstrDescrList = [reg.descr for reg in self.Instructionlist]
InstrExtList = [reg.Extension_Name for reg in self.Instructionlist]

r += "////\n"
r += " Copyright (c) 2024 OpenHW Group\n"
r += " Copyright (c) 2024 Thales\n"
r += " SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1\n"
r += " Author: Abdessamii Oukalrazqou\n"
r += "////\n\n"

r += "=== %s\n\n"%self.name
r += "==== Instructions\n\n"

r += "|===\n"
r += "|Subset Name | Name | Description\n\n"
for i, _ in enumerate(InstrNameList):
r += "|%s | %s | %s\n"%(str(InstrExtList[i]),
str(InstrNameList[i]),
str(InstrDescrList[i]).replace('\n',''))
r += "|===\n\n"

for reg in self.Instructionlist:
reg_table = []
if len(reg.Name) > 0:
r += "==== %s\n\n"%reg.key
r += "|===\n"
r += "| Name | Format | Pseudocode|Invalid_values | Exception_raised | Description| Op Name\n\n"

for fieldIndex in list(range(len(reg.Name))):
_line = [
reg.Name[fieldIndex],
reg.Format[fieldIndex],
reg.pseudocode[fieldIndex].replace('|','\|'),
reg.invalid_values[fieldIndex],
reg.exception_raised[fieldIndex],
reg.Description[fieldIndex],
]
_line.append(reg.OperationName[fieldIndex])

for col in _line:
r +="| %s "%col.replace('\n','')
r += "\n"
r += "|===\n\n"
return r

class InstmdBlock(InstructionBlockClass):
"""Generates an ISA Markdown file from a RISC Config Yaml register description"""
21 changes: 19 additions & 2 deletions config/gen_from_riscv_config/scripts/riscv_config_gen.py
Original file line number Diff line number Diff line change
@@ -23,8 +23,10 @@
from libs.utils import IsaGenerator
from libs.utils import CsrGenerator
from libs.utils import RstAddressBlock
from libs.utils import AdocAddressBlock
from libs.utils import MdAddressBlock
from libs.utils import InstrstBlock
from libs.utils import InstadocBlock
from libs.utils import InstmdBlock

if __name__ == "__main__":
@@ -35,13 +37,28 @@
parser.add_argument("-m", "--modif", help="ISA /CSR Formatter if exist")
parser.add_argument("-i", "--temp", help="Full ISA /SPIKETemplate")
parser.add_argument("-t", "--target", help="Specifiy Config Name")
parser.add_argument("-f", "--format", help="Specifiy format output")
args, unknown_args = parser.parse_known_args()

if args.format in ['rst']:
C_instrBlock = InstrstBlock
C_AddressBlock = RstAddressBlock
elif args.format in ['adoc']:
C_instrBlock = InstadocBlock
C_AddressBlock = AdocAddressBlock
elif args.format in ['md']:
C_instrBlock = InstmdBlock
C_AddressBlock = MdAddressBlock
else:
C_instrBlock = InstrstBlock
C_AddressBlock = RstAddressBlock

if args.temp:
if "isa" in args.temp:
e = IsaParser(args.srcFile, args.temp, args.target, args.modif)
document = e.returnDocument()
generator = IsaGenerator(args.target)
generator.generateISA(InstrstBlock, document)
generator.generateISA(C_instrBlock, document)
elif "spike" in args.temp:
e = SpikeParser(args.srcFile, args.target)
document = e.returnDocument()
@@ -51,4 +68,4 @@
e = CsrParser(args.srcFile, args.customFile, args.target, args.modif)
document = e.returnDocument()
generator = CsrGenerator(args.target)
generator.generateCSR(RstAddressBlock, document)
generator.generateCSR(C_AddressBlock, document)
Original file line number Diff line number Diff line change
@@ -47,3 +47,5 @@
:MTvalEn: false
:MTvecDirectEn: true
:note: false
:DebugEn: false
:MmuPresent: false
44 changes: 8 additions & 36 deletions docs/04_cv32a65x/design/Makefile
Original file line number Diff line number Diff line change
@@ -1,38 +1,10 @@
# Copyright 2024 Thales DIS France SAS
# Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
# you may not use this file except in compliance with the License.
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
# You may obtain a copy of the License at https://solderpad.org/licenses/
#
# Copyright (c) 2020 OpenHW Group
#
# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# https://solderpad.org/licenses/
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
#
###############################################################################
#
# Minimal makefile for Sphinx documentation
#

# You can set these variables from the command line.
SPHINXOPTS =
SPHINXBUILD = sphinx-build
SOURCEDIR = source
BUILDDIR = build

# Put it first so that "make" without argument is like "make help".
help:
@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)

.PHONY: help Makefile
# Original Author: Thales DIS

# Catch-all target: route all unknown targets to Sphinx using the new
# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
%: Makefile
@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
CONFIG := cv32a65x
include ../../design/build.mk
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