Branch feature/interconnect: fetch upstream

.github/workflows/ci.yml

@@ -42,7 +42,9 @@ jobs:
           cache-name: cache-spike
       with:
           path: tools/spike/
-          key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ hashFiles('verif/regress/install-spike.sh', 'verif/core-v-verif/vendor/riscv/') }}
+          key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ hashFiles('verif/regress/install-spike.sh',
+              'verif/core-v-verif/vendor/riscv/riscv-isa-sim/**/*',
+              'verif/core-v-verif/vendor/riscv/riscv-isa-sim/*') }}
 
     - name: Prepare
       run: |
@@ -95,7 +97,9 @@ jobs:
           cache-name: cache-spike
       with:
           path: tools/spike/
-          key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ hashFiles('verif/regress/install-spike.sh', 'verif/core-v-verif/vendor/riscv/') }}
+          key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ hashFiles('verif/regress/install-spike.sh',
+              'verif/core-v-verif/vendor/riscv/riscv-isa-sim/**/*',
+              'verif/core-v-verif/vendor/riscv/riscv-isa-sim/*') }}
 
     - name: Run Tests
       run: |
@@ -155,7 +159,9 @@ jobs:
           cache-name: cache-spike
       with:
           path: tools/spike/
-          key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ hashFiles('verif/regress/install-spike.sh', 'verif/core-v-verif/vendor/riscv/') }}
+          key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ hashFiles('verif/regress/install-spike.sh',
+              'verif/core-v-verif/vendor/riscv/riscv-isa-sim/**/*',
+              'verif/core-v-verif/vendor/riscv/riscv-isa-sim/*') }}
 
     - name: Run Tests
       run: |

.gitignore

@@ -19,6 +19,7 @@ build/*
 /Bender.local
 build/
 *.vcd
+*.fsdb
 *.log
 *.out
 *.jou

.gitlab-ci.yml

@@ -228,24 +228,24 @@ asic-synthesis:
     DASHBOARD_JOB_DESCRIPTION: "Synthesis indicator with specific Techno"
     DASHBOARD_SORT_INDEX: 5
     DASHBOARD_JOB_CATEGORY: "Synthesis"
-    INPUT_DELAY: "0.46"
-    OUTPUT_DELAY: "0.11"
-    PERIOD: "0.85"
-    DV_TARGET: "cv32a6_embedded"
+    PERIOD: "15"
+    DV_TARGET: cv32a65x
   script:
-    - echo $SYNTH_PERIOD
-    - echo $INPUT_DELAY
-    - echo $OUTPUT_DELAY
-    - echo $NAND2_AREA
-    - echo $FOUNDRY_PATH
     - echo $PERIOD
-    - echo $TECH_NAME
     - echo $DV_TARGET
     - source ./verif/sim/setup-env.sh
+    - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH}
+    - cp -r ${SYNTH_SCRIPT_PATH}/cva6/ ../
+    - git apply ${SYNTH_SCRIPT_PATH}/patches/*.patch
     - echo $SYN_DCSHELL_BASHRC; source $SYN_DCSHELL_BASHRC
-    - make -C pd/synth cva6_synth TARGET="$DV_TARGET"
-    - mv pd/synth/cva6_${DV_TARGET}_synth_modified.v artifacts/cva6_${DV_TARGET}_synth_modified.v
-    - python3 .gitlab-ci/scripts/report_synth.py pd/synth/cva6_${DV_TARGET}/reports/$PERIOD/cva6_$(echo $TECH_NAME)_synth_area.rpt pd/synth/synthesis_batch.log
+    - cp -r ${SYNTH_FLOW} ./
+    - python3 ${SYNTH_SCRIPT_PATH}/scharm -p configs/modules/CVA6.yml --runner=True --compaign="only-synth"
+    - export NAND2_AREA=$(cat pd/synth/cva6_${DV_TARGET}/nand2area.txt)
+    - python3 .gitlab-ci/scripts/report_synth.py pd/synth/cva6_${DV_TARGET}/$PERIOD/reports/cva6_${DV_TARGET}_synth_area.rpt pd/synth/cva6_${DV_TARGET}/$PERIOD/reports/cva6_${DV_TARGET}_synthesis.log
+    - mv ${SYNTH_SCRIPT_PATH}/artifacts/ artifacts/artifacts_synth/
+    - mv pd/synth/cva6_${DV_TARGET}/ artifacts/
+    - mv pd/synth/cva6_${DV_TARGET}_synth.v artifacts/
+    - mv pd/synth/cva6_${DV_TARGET}_synth.sdf artifacts/
 
 fpga-build:
   extends:
@@ -454,33 +454,41 @@ csr_embedded_tests:
     - mkdir -p artifacts/{reports,logs}
     - python3 .gitlab-ci/scripts/report_fail.py
 
-smoke-gate:
+simu-gate:
+  timeout : 4 hours
   extends:
     - .backend_test
   needs:
     - build_tools
     - asic-synthesis
+  parallel:
+    matrix:
+      - SIMU_PERIOD: ["20"]  # 50 Mhz
+        PERIOD:      ["15"]  # 66 Mhz
   variables:
-    DV_TARGET: cv32a6_embedded
-    DASHBOARD_JOB_TITLE: "Smoke Gate $DV_TARGET"
-    DASHBOARD_JOB_DESCRIPTION: "Simple test to check netlist from ASIC synthesis"
+    DASHBOARD_JOB_TITLE: "Gate Level Simulation $DV_TARGET"
+    DASHBOARD_JOB_DESCRIPTION: "Tests to check netlist from ASIC synthesis and power consumption over different patterns"
     DASHBOARD_SORT_INDEX: 6
     DASHBOARD_JOB_CATEGORY: "Post Synthesis"
+    DV_TARGET: cv32a65x
+    TARGET: $DV_TARGET
   script:
     - git -C verif/core-v-verif fetch --unshallow
     - mkdir -p tools
     - mv artifacts/tools/spike tools
     - echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC
-    - echo $LIB_VERILOG
-    - echo $FOUNDRY_PATH
     - echo $PERIOD
-    - echo $TECH_NAME
     - source ./verif/sim/setup-env.sh
+    - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH}
+    - cp -r ${SYNTH_SCRIPT_PATH}/cva6/ ../
+    - git apply ${SYNTH_SCRIPT_PATH}/patches/*.patch
     - source verif/regress/install-riscv-tests.sh
-    - mv artifacts/cva6_${DV_TARGET}_synth_modified.v pd/synth/cva6_${DV_TARGET}_synth_modified.v
-    - cd verif/sim
-    - make vcs_clean_all
-    - python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-lw --iss_yaml cva6.yaml --target $DV_TARGET --iss=spike,vcs-gate $DV_OPTS
+    - mv artifacts/cva6_${DV_TARGET} pd/synth/
+    - mv artifacts/cva6_${DV_TARGET}_synth.v pd/synth/
+    - mv artifacts/cva6_${DV_TARGET}_synth.sdf pd/synth/
+    - mkdir -p pd/synth/cva6_${DV_TARGET}/outputs/
+    - python3 ${SYNTH_SCRIPT_PATH}/scharm -p configs/modules/CVA6.yml --runner=True --compaign="simu-gate" --name=$PROG_NAME
+    - mv ${SYNTH_SCRIPT_PATH}/artifacts/ artifacts/artifacts_gate/
   after_script: *simu_after_script
 
 fpga-boot:

.gitlab-ci/expected_synth.yml

@@ -1,4 +1,4 @@
 cv32a6_embedded:
   gates: 110095
 cv32a65x:
-  gates: 109555
+  gates: 128136

.gitlab-ci/scripts/report_coverage.py

@@ -43,7 +43,6 @@ def get_fc_scores(component):
 	"controller_i",
 	"csr_regfile_i",
 	"ex_stage_i",
-	"gen_cache_hpd.i_cache_subsystem",
 	"i_frontend",
 	"id_stage_i",
 	"issue_stage_i",

.gitlab-ci/scripts/report_synth.py

@@ -20,6 +20,9 @@
 with open(str(sys.argv[2]), 'r') as f:
     synthesis_log = f.read()
 
+ignored_warning = ["RM-Error", "TFCHK-014", "TFCHK-012", "TFCHK-049",
+                    "MV-021", "MV-028", "TLUP-004", "TLUP-005",
+                    "TIM-164", "PWR-890", "PWR-80", "OPT-1413"]
 kgate_ratio = int(os.environ["NAND2_AREA"])
 path_re = r'^pd/synth/cva6_([^/]+)'
 with open(".gitlab-ci/expected_synth.yml", "r") as f:
@@ -30,6 +33,8 @@
 error_log = []
 warning_log = []
 for line in synthesis_log.splitlines():
+    if any (el in line for el in ignored_warning):
+        continue
     if os.environ['FOUNDRY_PATH'] in line:
         continue
     if os.environ['TECH_NAME'] in line:

Makefile

@@ -12,6 +12,8 @@ vcs-library    ?= work-vcs
 dpi-library    ?= work-dpi
 # Top level module to compile
 top_level      ?= ariane_tb
+# Top level path
+top_level_path ?= corev_apu/tb/$(top_level).sv
 # Maximum amount of cycles for a successful simulation run
 max_cycles     ?= 10000000
 # Test case to run
@@ -222,7 +224,7 @@ fpga_src :=  $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/a
 fpga_src := $(addprefix $(root-dir), $(fpga_src)) src/bootrom/bootrom_$(XLEN).sv
 
 # look for testbenches
-tbs := corev_apu/tb/ariane_tb.sv corev_apu/tb/ariane_testharness.sv core/cva6_rvfi.sv
+tbs := $(top_level_path) corev_apu/tb/ariane_testharness.sv core/cva6_rvfi.sv
 
 tbs := $(addprefix $(root-dir), $(tbs))
 
@@ -258,7 +260,7 @@ compile_flag     += -incr -64 -nologo -quiet -suppress 13262 -suppress 8607 -per
 vopt_flag += -suppress 2085 -suppress 7063 -suppress 2698 -suppress 13262
 
 uvm-flags        += +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-questa-flags     += -t 1ns -64 $(gui-sim) $(QUESTASIM_FLAGS) +tohost_addr=$(tohost_addr) +define+QUESTA -suppress 3356
+questa-flags     += -t 1ns -64 $(gui-sim) $(QUESTASIM_FLAGS) +tohost_addr=$(tohost_addr) +define+QUESTA -suppress 3356 -suppress 3579
 compile_flag_vhd += -64 -nologo -quiet -2008
 
 # Iterate over all include directories and write them with +incdir+ prefixed
@@ -298,16 +300,19 @@ else
 	questa-cmd += +jtag_rbb_enable=0
 endif
 
+flist ?= core/Flist.cva6
+
 vcs_build: $(dpi-library)/ariane_dpi.so
 	mkdir -p $(vcs-library)
 	cd $(vcs-library) &&\
-	vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog +define+$(defines) -assert svaext -f ../core/Flist.cva6 $(list_incdir) &&\
+	vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog +define+$(defines) -assert svaext -f $(flist) $(list_incdir) ../corev_apu/tb/common/mock_uart.sv -timescale=1ns/1ns &&\
 	vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog +define+$(defines) $(filter %.sv,$(ariane_pkg)) +incdir+core/include/+$(VCS_HOME)/etc/uvm-1.2/dpi &&\
 	vhdlan $(if $(VERDI), -kdb,) -full64 -nc $(filter %.vhd,$(uart_src)) &&\
 	vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -assert svaext +define+$(defines) +incdir+$(VCS_HOME)/etc/uvm/src $(VCS_HOME)/etc/uvm/src/uvm_pkg.sv  $(filter %.sv,$(src)) $(list_incdir) &&\
 	vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 &&\
 	vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 $(tbs) +define+$(defines) $(list_incdir) &&\
-	vcs $(if $(DEBUG), -debug_access+all $(if $(VERDI), -kdb),) $(if $(TRACE_COMPACT),+vcs+fsdbon) -full64 -timescale=1ns/1ns -ntb_opts uvm-1.2 work.ariane_tb -error="IWNF"
+	vcs $(if $(DEBUG), -debug_access+all $(if $(VERDI), -kdb),) $(if $(TRACE_COMPACT),+vcs+fsdbon) -ignore initializer_driver_checks -timescale=1ns/1ns -ntb_opts uvm-1.2 work.$(top_level) -error="IWNF" \
+	$(if $(gate), -sdf Max:ariane_gate_tb.i_ariane.i_cva6:$(CVA6_REPO_DIR)/pd/synth/cva6_$(TARGET)_synth.sdf +neg_tchk, +notimingcheck)
 
 vcs: vcs_build
 	cd $(vcs-library) && \

ci/setup.sh

@@ -21,7 +21,7 @@ if [ -d ${VERILATOR_BUILD_DIR} ]; then
 fi
 
 if [ -f ${SPIKE_PATH}/spike ]; then
-    spike_version="$(git -C ${SPIKE_SRC_DIR} log -1 --pretty=tformat:%h -- ${SPIKE_SRC_DIR}/ )"
+    spike_version="$(git -C ${SPIKE_SRC_DIR} log -1 --pretty=tformat:%h )"
     spike_installed_version="$(${SPIKE_PATH}/spike -v |& cut -d ' ' -f 2)"
     if [ "$spike_installed_version" != "$spike_version" ]; then
         rm -rf ${SPIKE_INSTALL_DIR}

common/local/util/sram.sv

@@ -48,6 +48,7 @@ logic [BE_WIDTH_ALIGNED-1:0]    be_aligned;
 logic [DATA_WIDTH_ALIGNED-1:0]  rdata_aligned;
 logic [USER_WIDTH_ALIGNED-1:0]  ruser_aligned;
 
+
 // align to 64 bits for inferrable macro below
 always_comb begin : p_align
     wdata_aligned                    ='0;
@@ -100,8 +101,17 @@ end
             .addr_i   ( addr_i                    ),
             .rdata_o  ( ruser_aligned[k*64 +: 64] )
         );
-      end else begin
-        assign ruser_aligned[k*64 +: 64] = '0;
+      end else begin : gen_mem_user
+          assign ruser_aligned[k*64 +: 64] = '0;
+          // synthesis translate_off
+          begin: i_tc_sram_wrapper_user
+            begin: i_tc_sram
+              logic init_val;
+              localparam type data_t = logic [63:0];
+              data_t sram [NUM_WORDS-1:0] /* verilator public_flat */;
+            end
+          end
+          // synthesis translate_on
       end
   end
 endmodule : sram

common/local/util/sram_cache.sv

@@ -0,0 +1,126 @@
+// Copyright 2018 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+//
+// Author: Florian Zaruba    <[email protected]>, ETH Zurich
+//         Michael Schaffner <[email protected]>, ETH Zurich
+// Date: 15.08.2018
+// Description: SRAM wrapper for FPGA (requires the fpga-support submodule)
+//
+// Note: the wrapped module contains two different implementations for
+// ALTERA and XILINX tools, since these follow different coding styles for
+// inferrable RAMS with byte enable. define `FPGA_TARGET_XILINX or
+// `FPGA_TARGET_ALTERA in your build environment (default is ALTERA)
+
+module sram_cache #(
+    parameter DATA_WIDTH = 64,
+    parameter USER_WIDTH = 1,
+    parameter USER_EN    = 0,
+    parameter NUM_WORDS  = 1024,
+    parameter SIM_INIT   = "none",
+    parameter BYTE_ACCESS = 1,
+    parameter TECHNO_CUT = 0,
+    parameter OUT_REGS   = 0     // enables output registers in FPGA macro (read lat = 2)
+)(
+   input  logic                          clk_i,
+   input  logic                          rst_ni,
+   input  logic                          req_i,
+   input  logic                          we_i,
+   input  logic [$clog2(NUM_WORDS)-1:0]  addr_i,
+   input  logic [USER_WIDTH-1:0]         wuser_i,
+   input  logic [DATA_WIDTH-1:0]         wdata_i,
+   input  logic [(DATA_WIDTH+7)/8-1:0]   be_i,
+   output logic [USER_WIDTH-1:0]         ruser_o,
+   output logic [DATA_WIDTH-1:0]         rdata_o
+);
+  localparam DATA_AND_USER_WIDTH = USER_EN ? DATA_WIDTH + USER_WIDTH : DATA_WIDTH;
+  if (TECHNO_CUT) begin : gen_techno_cut
+    if (USER_EN > 0) begin
+      logic [DATA_WIDTH + USER_WIDTH-1:0] wdata_user;
+      logic [DATA_WIDTH + USER_WIDTH-1:0] rdata_user;
+      logic [(DATA_WIDTH+7)/8+(DATA_WIDTH+7)/8-1:0] be;
+
+      always_comb begin
+        wdata_user = {wdata_i, wuser_i};
+        be         = {be_i, be_i};
+        rdata_o    = rdata_user[DATA_AND_USER_WIDTH-1:DATA_WIDTH];
+        ruser_o    = rdata_user[USER_WIDTH-1:0];
+      end
+      tc_sram_wrapper_cache_techno #(
+        .NumWords(NUM_WORDS),           // Number of Words in data array
+        .DataWidth(DATA_AND_USER_WIDTH),// Data signal width
+        .ByteWidth(32'd8),              // Width of a data byte
+        .NumPorts(32'd1),               // Number of read and write ports
+        .Latency(32'd1),                // Latency when the read data is available
+        .SimInit(SIM_INIT),             // Simulation initialization
+        .BYTE_ACCESS(BYTE_ACCESS),      // ACCESS byte or full word
+        .PrintSimCfg(1'b0)              // Print configuration
+      ) i_tc_sram_wrapper (
+        .clk_i    ( clk_i                     ),
+        .rst_ni   ( rst_ni                    ),
+        .req_i    ( req_i                     ),
+        .we_i     ( we_i                      ),
+        .be_i     ( be                        ),
+        .wdata_i  ( wdata_user                ),
+        .addr_i   ( addr_i                    ),
+        .rdata_o  ( rdata_user                )
+      );
+    end else begin
+      logic [DATA_WIDTH-1:0] wdata_user;
+      logic [DATA_WIDTH-1:0] rdata_user;
+      logic [(DATA_WIDTH+7)/8-1:0] be;
+
+      always_comb begin
+        wdata_user = wdata_i;
+        be         = be_i;
+        rdata_o    = rdata_user;
+        ruser_o    = '0;
+      end
+      tc_sram_wrapper_cache_techno #(
+        .NumWords(NUM_WORDS),           // Number of Words in data array
+        .DataWidth(DATA_AND_USER_WIDTH),// Data signal width
+        .ByteWidth(32'd8),              // Width of a data byte
+        .NumPorts(32'd1),               // Number of read and write ports
+        .Latency(32'd1),                // Latency when the read data is available
+        .SimInit(SIM_INIT),             // Simulation initialization
+        .BYTE_ACCESS(BYTE_ACCESS),      // ACCESS byte or full word
+        .PrintSimCfg(1'b0)              // Print configuration
+      ) i_tc_sram_wrapper (
+        .clk_i    ( clk_i                     ),
+        .rst_ni   ( rst_ni                    ),
+        .req_i    ( req_i                     ),
+        .we_i     ( we_i                      ),
+        .be_i     ( be                        ),
+        .wdata_i  ( wdata_user                ),
+        .addr_i   ( addr_i                    ),
+        .rdata_o  ( rdata_user                )
+      );
+    end
+  end else begin
+    sram #(
+          .USER_WIDTH (USER_WIDTH),
+          .DATA_WIDTH (DATA_WIDTH),
+          .USER_EN    (USER_EN),
+          .NUM_WORDS  (NUM_WORDS)
+      ) data_sram (
+          .clk_i  (clk_i),
+          .rst_ni (rst_ni),
+          .req_i  (req_i),
+          .we_i   (we_i),
+          .addr_i (addr_i),
+          .wuser_i(wuser_i),
+          .wdata_i(wdata_i),
+          .be_i   (be_i),
+          .ruser_o(ruser_o),
+          .rdata_o(rdata_o)
+      );
+  end
+
+
+endmodule : sram_cache