Parametrization step 2

common/local/util/ex_trace_item.svh

@@ -13,7 +13,10 @@
 // Description: Instruction tracer single exception item
 
 `ifndef VERILATOR
-class ex_trace_item;
+class ex_trace_item #(
+    parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
+);
+
     // contains a human readable form of the cause value
     string                  cause_s;
     logic [63:0]            cause;

common/local/util/instr_trace_item.svh

@@ -22,11 +22,15 @@ function string printPCexpr(input logic [63:0] imm);
   end
 endfunction
 
-class instr_trace_item;
+class instr_trace_item #(
+    parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
+    parameter type bp_resolve_t = logic,
+    parameter type scoreboard_entry_t = logic
+);
     // keep a couple of general purpose information inside this instruction item
     time               simtime;
     longint unsigned   cycle;
-    ariane_pkg::scoreboard_entry_t sbe;
+    scoreboard_entry_t sbe;
     logic [31:0]       pc;
     logic [31:0]       instr;
     logic [63:0]       gp_reg_file [32];
@@ -39,13 +43,13 @@ class instr_trace_item;
     logic [63:0]       result;
     logic [riscv::PLEN-1:0]       paddr;
     string             priv_lvl;
-    ariane_pkg::bp_resolve_t       bp;
+    bp_resolve_t       bp;
 
     logic [4:0] rs1, rs2, rs3, rd;
 
     // constructor creating a new instruction trace item, e.g.: a single instruction with all relevant information
-    function new (time simtime, longint unsigned cycle, ariane_pkg::scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] gp_reg_file [32],
-                logic [63:0] fp_reg_file [32], logic [63:0] result, logic [riscv::PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, ariane_pkg::bp_resolve_t bp);
+    function new (time simtime, longint unsigned cycle, scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] gp_reg_file [32],
+                logic [63:0] fp_reg_file [32], logic [63:0] result, logic [riscv::PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, bp_resolve_t bp);
         this.simtime  = simtime;
         this.cycle    = cycle;
         this.pc       = sbe.pc;

common/local/util/instr_tracer.sv

@@ -17,8 +17,12 @@
 `include "ex_trace_item.svh"
 `include "instr_trace_item.svh"
 
-module instr_tracer (
-  instr_tracer_if   tracer_if,
+module instr_tracer #(
+  parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
+  parameter type bp_resolve_t = logic,
+  parameter type scoreboard_entry_t = logic
+)(
+  instr_tracer_if tracer_if,
   input logic[riscv::XLEN-1:0] hart_id_i
 );
 
@@ -27,10 +31,10 @@ module instr_tracer (
   // keep the issued instructions in a queue
   logic [31:0] issue_queue [$];
   // issue scoreboard entries
-  ariane_pkg::scoreboard_entry_t issue_sbe_queue [$];
-  ariane_pkg::scoreboard_entry_t issue_sbe;
+  scoreboard_entry_t issue_sbe_queue [$];
+  scoreboard_entry_t issue_sbe;
   // store resolved branches, get (mis-)predictions
-  ariane_pkg::bp_resolve_t bp [$];
+  bp_resolve_t bp [$];
   // shadow copy of the register files
   logic [63:0] gp_reg_file [32];
   logic [63:0] fp_reg_file [32];
@@ -55,13 +59,13 @@ module instr_tracer (
 
   task trace();
     automatic logic [31:0] decode_instruction, issue_instruction, issue_commit_instruction;
-    automatic ariane_pkg::scoreboard_entry_t commit_instruction;
+    automatic scoreboard_entry_t commit_instruction;
     // initialize register 0
     gp_reg_file  = '{default:0};
     fp_reg_file  = '{default:0};
 
     forever begin
-      automatic ariane_pkg::bp_resolve_t bp_instruction = '0;
+      automatic bp_resolve_t bp_instruction = '0;
       // new cycle, we are only interested if reset is de-asserted
       @(tracer_if.pck) if (tracer_if.pck.rstn !== 1'b1) begin
         flush();
@@ -88,7 +92,7 @@ module instr_tracer (
         issue_instruction = decode_queue.pop_front();
         issue_queue.push_back(issue_instruction);
         // also save the scoreboard entry to a separate issue queue
-        issue_sbe_queue.push_back(ariane_pkg::scoreboard_entry_t'(tracer_if.pck.issue_sbe));
+        issue_sbe_queue.push_back(scoreboard_entry_t'(tracer_if.pck.issue_sbe));
       end
 
       // --------------------
@@ -113,7 +117,7 @@ module instr_tracer (
       // we are committing an instruction
       for (int i = 0; i < 2; i++) begin
         if (tracer_if.pck.commit_ack[i]) begin
-          commit_instruction = ariane_pkg::scoreboard_entry_t'(tracer_if.pck.commit_instr[i]);
+          commit_instruction = scoreboard_entry_t'(tracer_if.pck.commit_instr[i]);
           issue_commit_instruction = issue_queue.pop_front();
           issue_sbe = issue_sbe_queue.pop_front();
           // check if the instruction retiring is a load or store, get the physical address accordingly
@@ -186,8 +190,12 @@ module instr_tracer (
     bp              = {};
   endfunction
 
-  function void printInstr(ariane_pkg::scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] result, logic [riscv::PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, ariane_pkg::bp_resolve_t bp);
-    automatic instr_trace_item iti = new ($time, clk_ticks, sbe, instr, gp_reg_file, fp_reg_file, result, paddr, priv_lvl, debug_mode, bp);
+  function void printInstr(scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] result, logic [riscv::PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, bp_resolve_t bp);
+    automatic instr_trace_item #(
+      .CVA6Cfg(CVA6Cfg),
+      .bp_resolve_t(bp_resolve_t),
+      .scoreboard_entry_t(scoreboard_entry_t)
+    ) iti = new ($time, clk_ticks, sbe, instr, gp_reg_file, fp_reg_file, result, paddr, priv_lvl, debug_mode, bp);
     // print instruction to console
     automatic string print_instr = iti.printInstr();
     if (ariane_pkg::ENABLE_SPIKE_COMMIT_LOG && !debug_mode) begin
@@ -197,7 +205,9 @@ module instr_tracer (
   endfunction
 
   function void printException(logic [riscv::VLEN-1:0] pc, logic [63:0] cause, logic [63:0] tval);
-    automatic ex_trace_item eti = new (pc, cause, tval);
+    automatic ex_trace_item #(
+      .CVA6Cfg(CVA6Cfg)
+    ) eti = new (pc, cause, tval);
     automatic string print_ex = eti.printException();
     $fwrite(f, {print_ex, "\n"});
   endfunction

common/local/util/instr_tracer_if.sv

@@ -15,7 +15,12 @@
 `ifndef VERILATOR
 `ifndef INSTR_TRACER_IF_SV
 `define INSTR_TRACER_IF_SV
-interface instr_tracer_if (
+interface instr_tracer_if #(
+  parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
+  parameter type bp_resolve_t = logic,
+  parameter type exception_t = logic,
+  parameter type scoreboard_entry_t = logic
+)(
         input clk
     );
 
@@ -28,14 +33,14 @@ interface instr_tracer_if (
     logic             fetch_ack;
     // Issue stage
     logic                           issue_ack; // issue acknowledged
-    ariane_pkg::scoreboard_entry_t  issue_sbe; // issue scoreboard entry
+    scoreboard_entry_t  issue_sbe; // issue scoreboard entry
     // WB stage
     logic [1:0][4:0]  waddr;
     logic [1:0][63:0] wdata;
     logic [1:0]       we_gpr;
     logic [1:0]       we_fpr;
     // commit stage
-    ariane_pkg::scoreboard_entry_t [1:0] commit_instr; // commit instruction
+    scoreboard_entry_t [1:0] commit_instr; // commit instruction
     logic                          [1:0] commit_ack;
     // address translation
     // stores
@@ -46,9 +51,9 @@ interface instr_tracer_if (
     logic                         ld_kill;
     logic [riscv::PLEN-1:0]       ld_paddr;
     // misprediction
-    ariane_pkg::bp_resolve_t resolve_branch;
+    bp_resolve_t resolve_branch;
     // exceptions
-    ariane_pkg::exception_t  exception;
+    exception_t exception;
     // current privilege level
     riscv::priv_lvl_t  priv_lvl;
     logic              debug_mode;

core/Flist.cva6

@@ -67,7 +67,6 @@ ${CVA6_REPO_DIR}/vendor/pulp-platform/axi/src/axi_pkg.sv
 ${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv
 ${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv
 ${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
-${CVA6_REPO_DIR}/core/include/acc_pkg.sv
 ${CVA6_REPO_DIR}/core/include/build_config_pkg.sv
 
 //CVXIF

core/acc_dispatcher.sv

@@ -17,11 +17,44 @@ module acc_dispatcher
   import ariane_pkg::*;
   import riscv::*;
 #(
-    parameter config_pkg::cva6_cfg_t CVA6Cfg    = config_pkg::cva6_cfg_empty,
-    parameter type                   acc_req_t  = acc_pkg::accelerator_req_t,
-    parameter type                   acc_resp_t = acc_pkg::accelerator_resp_t,
-    parameter type                   acc_cfg_t  = logic,
-    parameter acc_cfg_t              AccCfg     = '0
+    parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
+    parameter type dcache_req_i_t = logic,
+    parameter type dcache_req_o_t = logic,
+    parameter type exception_t = logic,
+    parameter type fu_data_t = logic,
+    parameter type scoreboard_entry_t = logic,
+    localparam type accelerator_req_t = struct packed {
+      logic                                 req_valid;
+      logic                                 resp_ready;
+      riscv::instruction_t                  insn;
+      riscv::xlen_t                         rs1;
+      riscv::xlen_t                         rs2;
+      fpnew_pkg::roundmode_e                frm;
+      logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id;
+      logic                                 store_pending;
+      // Invalidation interface
+      logic                                 acc_cons_en;
+      logic                                 inval_ready;
+    },
+    parameter type acc_req_t = accelerator_req_t,
+    parameter type acc_resp_t = struct packed {
+      logic                                 req_ready;
+      logic                                 resp_valid;
+      riscv::xlen_t                         result;
+      logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id;
+      logic                                 error;
+      // Metadata
+      logic                                 store_pending;
+      logic                                 store_complete;
+      logic                                 load_complete;
+      logic [4:0]                           fflags;
+      logic                                 fflags_valid;
+      // Invalidation interface
+      logic                                 inval_valid;
+      logic [63:0]                          inval_addr;
+    },
+    parameter type acc_cfg_t = logic,
+    parameter acc_cfg_t AccCfg = '0
 ) (
     input logic clk_i,
     input logic rst_ni,
@@ -190,13 +223,13 @@ module acc_dispatcher
    *  Accelerator request  *
    *************************/
 
-  acc_pkg::accelerator_req_t acc_req;
-  logic                      acc_req_valid;
-  logic                      acc_req_ready;
+  accelerator_req_t acc_req;
+  logic             acc_req_valid;
+  logic             acc_req_ready;
 
-  acc_pkg::accelerator_req_t acc_req_int;
+  accelerator_req_t acc_req_int;
   fall_through_register #(
-      .T(acc_pkg::accelerator_req_t)
+      .T(accelerator_req_t)
   ) i_accelerator_req_register (
       .clk_i     (clk_i),
       .rst_ni    (rst_ni),

core/alu.sv

@@ -21,7 +21,8 @@
 module alu
   import ariane_pkg::*;
 #(
-    parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
+    parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
+    parameter type fu_data_t = logic
 ) (
     // Subsystem Clock - SUBSYSTEM
     input logic clk_i,

core/branch_unit.sv

@@ -13,7 +13,11 @@
 // Description: Branch target calculation and comparison
 
 module branch_unit #(
-    parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
+    parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
+    parameter type bp_resolve_t = logic,
+    parameter type branchpredict_sbe_t = logic,
+    parameter type exception_t = logic,
+    parameter type fu_data_t = logic
 ) (
     // Subsystem Clock - SUBSYSTEM
     input logic clk_i,
@@ -22,7 +26,7 @@ module branch_unit #(
     // Debug mode state - CSR_REGFILE
     input logic debug_mode_i,
     // FU data needed to execute instruction - ISSUE_STAGE
-    input ariane_pkg::fu_data_t fu_data_i,
+    input fu_data_t fu_data_i,
     // Instruction PC - ISSUE_STAGE
     input logic [riscv::VLEN-1:0] pc_i,
     // Instruction is compressed - ISSUE_STAGE
@@ -36,13 +40,13 @@ module branch_unit #(
     // Brach unit result - ISSUE_STAGE
     output logic [riscv::VLEN-1:0] branch_result_o,
     // Information of branch prediction - ISSUE_STAGE
-    input ariane_pkg::branchpredict_sbe_t branch_predict_i,
+    input branchpredict_sbe_t branch_predict_i,
     // Signaling that we resolved the branch - ISSUE_STAGE
-    output ariane_pkg::bp_resolve_t resolved_branch_o,
+    output bp_resolve_t resolved_branch_o,
     // Branch is resolved, new entries can be accepted by scoreboard - ID_STAGE
     output logic resolve_branch_o,
     // Branch exception out - TO_BE_COMPLETED
-    output ariane_pkg::exception_t branch_exception_o
+    output exception_t branch_exception_o
 );
   logic [riscv::VLEN-1:0] target_address;
   logic [riscv::VLEN-1:0] next_pc;

core/cache_subsystem/cache_ctrl.sv

@@ -22,7 +22,11 @@ module cache_ctrl
   import ariane_pkg::*;
   import std_cache_pkg::*;
 #(
-    parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
+    parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
+    parameter type cache_line_t = logic,
+    parameter type cl_be_t = logic,
+    parameter type dcache_req_i_t = logic,
+    parameter type dcache_req_o_t = logic
 ) (
     input logic clk_i,  // Clock
     input logic rst_ni,  // Asynchronous reset active low

core/cache_subsystem/cva6_hpdcache_if_adapter.sv

@@ -15,8 +15,10 @@ module cva6_hpdcache_if_adapter
 //  Parameters
 //  {{{
 #(
-    parameter config_pkg::cva6_cfg_t CVA6Cfg      = config_pkg::cva6_cfg_empty,
-    parameter bit                    is_load_port = 1'b1
+    parameter config_pkg::cva6_cfg_t CVA6Cfg        = config_pkg::cva6_cfg_empty,
+    parameter type                   dcache_req_i_t = logic,
+    parameter type                   dcache_req_o_t = logic,
+    parameter bit                    is_load_port   = 1'b1
 )
 //  }}}
 
@@ -31,10 +33,10 @@ module cva6_hpdcache_if_adapter
     input hpdcache_pkg::hpdcache_req_sid_t hpdcache_req_sid_i,
 
     //  Request/response ports from/to the CVA6 core
-    input  ariane_pkg::dcache_req_i_t cva6_req_i,
-    output ariane_pkg::dcache_req_o_t cva6_req_o,
-    input  ariane_pkg::amo_req_t      cva6_amo_req_i,
-    output ariane_pkg::amo_resp_t     cva6_amo_resp_o,
+    input  dcache_req_i_t         cva6_req_i,
+    output dcache_req_o_t         cva6_req_o,
+    input  ariane_pkg::amo_req_t  cva6_amo_req_i,
+    output ariane_pkg::amo_resp_t cva6_amo_resp_o,
 
     //  Request port to the L1 Dcache
     output logic                        hpdcache_req_valid_o,