Complete Design Document #1865
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Complete Design Document #1865
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fix id_stage implement the black_list ports temporary Generate black list ports rename python script Black reformat
Fix BHT image
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core/alu.sv
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| // Asynchronous reset active low - SUBSYSTEM | ||
| input logic rst_ni, | ||
| // FU data needed to execute instruction - ISSUE_STAGE | ||
| input fu_data_t fu_data_i, |
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| input fu_data_t fu_data_i, | |
| input fu_data_t fu_data_i, |
core/branch_unit.sv
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| input logic is_compressed_instr_i, | ||
| input logic fu_valid_i, // any functional unit is valid, check that there is no accidental mis-predict | ||
| // any functional unit is valid, check that there is no accidental mis-predict - TO_BE_COMPLETED | ||
| input logic fu_valid_i, |
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| input logic fu_valid_i, | |
| input logic fu_valid_i, |
core/csr_buffer.sv
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| // CSR FU is ready - ISSUE_STAGE | ||
| output logic csr_ready_o, | ||
| // CSR instruction is valid - ISSUE_STAGE | ||
| input logic csr_valid_i, |
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| input logic csr_valid_i, | |
| input logic csr_valid_i, |
core/csr_buffer.sv
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| // CSR buffer result - ISSUE_STAGE | ||
| output riscv::xlen_t csr_result_o, | ||
| // commit the pending CSR OP - TO_BE_COMPLETED | ||
| input logic csr_commit_i, |
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| input logic csr_commit_i, | |
| input logic csr_commit_i, |
core/cvxif_fu.sv
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| input logic clk_i, | ||
| input logic rst_ni, | ||
| // Subsystem Clock - SUBSYSTEM | ||
| input logic clk_i, |
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| input logic clk_i, | |
| input logic clk_i, |
core/multiplier.sv
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| // Subsystem Clock - SUBSYSTEM | ||
| input logic clk_i, | ||
| // Asynchronous reset active low - SUBSYSTEM | ||
| input logic rst_ni, |
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[verible-verilog-format] reported by reviewdog 🐶
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| input logic rst_ni, | |
| input logic rst_ni, |
core/multiplier.sv
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| output logic mult_ready_o, | ||
| output logic [TRANS_ID_BITS-1:0] mult_trans_id_o | ||
| // Multiplier transaction ID - Mult | ||
| output logic [TRANS_ID_BITS-1:0] mult_trans_id_o |
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| output logic [TRANS_ID_BITS-1:0] mult_trans_id_o | |
| output logic [TRANS_ID_BITS-1:0] mult_trans_id_o |
core/scoreboard.sv
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| // RVFI | ||
| // Transaction ID at which to write the result back - TO_BE_COMPLETED | ||
| input logic [CVA6Cfg.NrWbPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0] trans_id_i, |
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[verible-verilog-format] reported by reviewdog 🐶
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| input logic [CVA6Cfg.NrWbPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0] trans_id_i, | |
| input logic [CVA6Cfg.NrWbPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0] trans_id_i, |
core/serdiv.sv
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| // handshake | ||
| input logic in_vld_i, // there is a cycle delay from in_rdy_o->in_vld_i, see issue_read_operands.sv stage | ||
| // Serdiv instruction is valid - Mult | ||
| input logic in_vld_i, |
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| input logic in_vld_i, | |
| input logic in_vld_i, |
core/store_unit.sv
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| input logic dtlb_hit_i, // will be one in the same cycle translation_req was asserted if it hits | ||
| // address checker | ||
| // Data TLB hit - lsu | ||
| input logic dtlb_hit_i, |
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[verible-verilog-format] reported by reviewdog 🐶
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| input logic dtlb_hit_i, | |
| input logic dtlb_hit_i, |
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✔️ successful run, report available here. |
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❌ failed run, report available here. |
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Thnaks to Côme for the review, this has improve the a lot the specification