Mmu unify 2

Bender.yml

@@ -48,29 +48,32 @@ sources:
           - core/include/cv32a6_imac_sv0_config_pkg.sv
           - core/include/riscv_pkg.sv
           - core/include/ariane_pkg.sv
-          - core/mmu_sv32/cva6_tlb_sv32.sv
-          - core/mmu_sv32/cva6_mmu_sv32.sv
+          - core/mmu_unify/cva6_tlb.sv
+          - core/mmu_unify/cva6_mmu.sv
           - core/mmu_sv32/cva6_ptw_sv32.sv
+          - core/mmu_unify/cva6_ptw.sv
           - core/cva6_accel_first_pass_decoder_stub.sv
 
       - target: cv32a6_imac_sv32
         files:
           - core/include/cv32a6_imac_sv32_config_pkg.sv
           - core/include/riscv_pkg.sv
           - core/include/ariane_pkg.sv
-          - core/mmu_sv32/cva6_tlb_sv32.sv
-          - core/mmu_sv32/cva6_mmu_sv32.sv
+          - core/mmu_unify/cva6_tlb.sv
+          - core/mmu_unify/cva6_mmu.sv
           - core/mmu_sv32/cva6_ptw_sv32.sv
+          - core/mmu_unify/cva6_ptw.sv
           - core/cva6_accel_first_pass_decoder_stub.sv
 
       - target: cv32a6_imafc_sv32
         files:
           - core/include/cv32a6_imafc_sv32_config_pkg.sv
           - core/include/riscv_pkg.sv
           - core/include/ariane_pkg.sv
-          - core/mmu_sv32/cva6_tlb_sv32.sv
-          - core/mmu_sv32/cva6_mmu_sv32.sv
+          - core/mmu_unify/cva6_tlb.sv
+          - core/mmu_unify/cva6_mmu.sv
           - core/mmu_sv32/cva6_ptw_sv32.sv
+          - core/mmu_unify/cva6_ptw.sv
           - core/cva6_accel_first_pass_decoder_stub.sv
 
       # included via target core/include/${TARGET_CFG}_config_pkg.sv

ariane.core

@@ -35,18 +35,21 @@ filesets:
       - src/miss_handler.sv
       - src/mmu_sv39/mmu.sv
       - src/mmu_sv32/cva6_mmu_sv32.sv
+      - src/mmu_unify/cva6_mmu.sv
       - src/mult.sv
       - src/nbdcache.sv
       - src/pcgen_stage.sv
       - src/perf_counters.sv
       - src/mmu_sv39/ptw.sv
       - src/mmu_sv32/cva6_ptw_sv32.sv
+      - src/mmu_unify/cva6_ptw.sv
       - src/regfile_ff.sv
       - src/scoreboard.sv
       - src/store_buffer.sv
       - src/store_unit.sv
       - src/mmu_sv39/tlb.sv
       - src/mmu_sv32/cva6_tlb_sv32.sv
+      - src/mmu_unify/cva6_tlb.sv
     file_type : systemVerilogSource
     depend :
       - pulp-platform.org::axi_mem_if

core/Flist.cva6

@@ -176,15 +176,10 @@ ${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv
 ${CVA6_REPO_DIR}/common/local/util/sram.sv
 
-// MMU Sv39
-${CVA6_REPO_DIR}/core/mmu_sv39/mmu.sv
-${CVA6_REPO_DIR}/core/mmu_sv39/ptw.sv
-${CVA6_REPO_DIR}/core/mmu_sv39/tlb.sv
-
-// MMU Sv32
-${CVA6_REPO_DIR}/core/mmu_sv32/cva6_mmu_sv32.sv
-${CVA6_REPO_DIR}/core/mmu_sv32/cva6_ptw_sv32.sv
-${CVA6_REPO_DIR}/core/mmu_sv32/cva6_tlb_sv32.sv
-${CVA6_REPO_DIR}/core/mmu_sv32/cva6_shared_tlb_sv32.sv
+// MMU Unify
+${CVA6_REPO_DIR}/core/mmu_unify/cva6_mmu.sv
+${CVA6_REPO_DIR}/core/mmu_unify/cva6_tlb.sv
+${CVA6_REPO_DIR}/core/mmu_unify/cva6_shared_tlb.sv
+${CVA6_REPO_DIR}/core/mmu_unify/cva6_ptw.sv
 
 // end of manifest

core/include/cv64a6_imafdc_sv39_config_pkg.sv

@@ -55,8 +55,8 @@ package cva6_config_pkg;
   localparam CVA6ConfigNrStorePipeRegs = 0;
   localparam CVA6ConfigNrLoadBufEntries = 2;
 
-  localparam CVA6ConfigInstrTlbEntries = 16;
-  localparam CVA6ConfigDataTlbEntries = 16;
+  localparam CVA6ConfigInstrTlbEntries = 2;
+  localparam CVA6ConfigDataTlbEntries = 2;
 
   localparam CVA6ConfigRASDepth = 2;
   localparam CVA6ConfigBTBEntries = 32;

core/include/riscv_pkg.sv

@@ -39,7 +39,9 @@ package riscv;
   // Warning: VLEN must be superior or equal to PLEN
   localparam VLEN = (XLEN == 32) ? 32 : 64;  // virtual address length
   localparam PLEN = (XLEN == 32) ? 34 : 56;  // physical address length
-
+  localparam GPLEN = (XLEN == 32) ? 34 : 41;
+  localparam GPPNW = (XLEN == 32) ? 22 : 29;
+  localparam GPPN2 = (XLEN == 32) ? riscv::VLEN - 33 : 10;
   localparam IS_XLEN32 = (XLEN == 32) ? 1'b1 : 1'b0;
   localparam IS_XLEN64 = (XLEN == 32) ? 1'b0 : 1'b1;
   localparam ModeW = (XLEN == 32) ? 1 : 4;
@@ -326,19 +328,24 @@ package riscv;
   // ----------------------
   localparam logic [XLEN-1:0] INSTR_ADDR_MISALIGNED = 0;
   localparam logic [XLEN-1:0] INSTR_ACCESS_FAULT    = 1;  // Illegal access as governed by PMPs and PMAs
-  localparam logic [XLEN-1:0] ILLEGAL_INSTR = 2;
-  localparam logic [XLEN-1:0] BREAKPOINT = 3;
-  localparam logic [XLEN-1:0] LD_ADDR_MISALIGNED = 4;
-  localparam logic [XLEN-1:0] LD_ACCESS_FAULT = 5;  // Illegal access as governed by PMPs and PMAs
-  localparam logic [XLEN-1:0] ST_ADDR_MISALIGNED = 6;
-  localparam logic [XLEN-1:0] ST_ACCESS_FAULT = 7;  // Illegal access as governed by PMPs and PMAs
-  localparam logic [XLEN-1:0] ENV_CALL_UMODE = 8;  // environment call from user mode
-  localparam logic [XLEN-1:0] ENV_CALL_SMODE = 9;  // environment call from supervisor mode
-  localparam logic [XLEN-1:0] ENV_CALL_MMODE = 11;  // environment call from machine mode
-  localparam logic [XLEN-1:0] INSTR_PAGE_FAULT = 12;  // Instruction page fault
-  localparam logic [XLEN-1:0] LOAD_PAGE_FAULT = 13;  // Load page fault
-  localparam logic [XLEN-1:0] STORE_PAGE_FAULT = 15;  // Store page fault
-  localparam logic [XLEN-1:0] DEBUG_REQUEST = 24;  // Debug request
+  localparam logic [XLEN-1:0] ILLEGAL_INSTR         = 2;
+  localparam logic [XLEN-1:0] BREAKPOINT            = 3;
+  localparam logic [XLEN-1:0] LD_ADDR_MISALIGNED    = 4;
+  localparam logic [XLEN-1:0] LD_ACCESS_FAULT       = 5;  // Illegal access as governed by PMPs and PMAs
+  localparam logic [XLEN-1:0] ST_ADDR_MISALIGNED    = 6;
+  localparam logic [XLEN-1:0] ST_ACCESS_FAULT       = 7;  // Illegal access as governed by PMPs and PMAs
+  localparam logic [XLEN-1:0] ENV_CALL_UMODE        = 8;  // environment call from user mode or virtual user mode
+  localparam logic [XLEN-1:0] ENV_CALL_SMODE        = 9;  // environment call from hypervisor-extended supervisor mode
+  localparam logic [XLEN-1:0] ENV_CALL_VSMODE       = 10; // environment call from virtual supervisor mode
+  localparam logic [XLEN-1:0] ENV_CALL_MMODE        = 11; // environment call from machine mode
+  localparam logic [XLEN-1:0] INSTR_PAGE_FAULT      = 12; // Instruction page fault
+  localparam logic [XLEN-1:0] LOAD_PAGE_FAULT       = 13; // Load page fault
+  localparam logic [XLEN-1:0] STORE_PAGE_FAULT      = 15; // Store page fault
+  localparam logic [XLEN-1:0] INSTR_GUEST_PAGE_FAULT= 20; // Instruction guest-page fault
+  localparam logic [XLEN-1:0] LOAD_GUEST_PAGE_FAULT = 21; // Load guest-page fault
+  localparam logic [XLEN-1:0] VIRTUAL_INSTRUCTION   = 22; // virtual instruction
+  localparam logic [XLEN-1:0] STORE_GUEST_PAGE_FAULT= 23; // Store guest-page fault
+  localparam logic [XLEN-1:0] DEBUG_REQUEST         = 24; // Debug request
 
   localparam int unsigned IRQ_S_SOFT = 1;
   localparam int unsigned IRQ_M_SOFT = 3;
@@ -361,6 +368,14 @@ package riscv;
   localparam logic [XLEN-1:0] S_EXT_INTERRUPT = (1 << (XLEN - 1)) | XLEN'(IRQ_S_EXT);
   localparam logic [XLEN-1:0] M_EXT_INTERRUPT = (1 << (XLEN - 1)) | XLEN'(IRQ_M_EXT);
 
+  // ----------------------
+  // PseudoInstructions Codes
+  // ----------------------
+  localparam logic [XLEN-1:0] READ_32_PSEUDOINSTRUCTION = 32'h00002000;
+  localparam logic [XLEN-1:0] WRITE_32_PSEUDOINSTRUCTION = 32'h00002020;
+  localparam logic [XLEN-1:0] READ_64_PSEUDOINSTRUCTION = 64'h00003000;
+  localparam logic [XLEN-1:0] WRITE_64_PSEUDOINSTRUCTION = 64'h00003020;
+
   // -----
   // CSRs
   // -----

core/load_store_unit.sv

@@ -140,63 +140,65 @@ module load_store_unit
   // -------------------
   // MMU e.g.: TLBs/PTW
   // -------------------
-  if (MMU_PRESENT && (riscv::XLEN == 64)) begin : gen_mmu_sv39
-    mmu #(
-        .CVA6Cfg          (CVA6Cfg),
-        .INSTR_TLB_ENTRIES(ariane_pkg::INSTR_TLB_ENTRIES),
-        .DATA_TLB_ENTRIES (ariane_pkg::DATA_TLB_ENTRIES),
-        .ASID_WIDTH       (ASID_WIDTH)
-    ) i_cva6_mmu (
-        // misaligned bypass
-        .misaligned_ex_i(misaligned_exception),
-        .lsu_is_store_i (st_translation_req),
-        .lsu_req_i      (translation_req),
-        .lsu_vaddr_i    (mmu_vaddr),
-        .lsu_valid_o    (translation_valid),
-        .lsu_paddr_o    (mmu_paddr),
-        .lsu_exception_o(mmu_exception),
-        .lsu_dtlb_hit_o (dtlb_hit),               // send in the same cycle as the request
-        .lsu_dtlb_ppn_o (dtlb_ppn),               // send in the same cycle as the request
-        // connecting PTW to D$ IF
-        .req_port_i     (dcache_req_ports_i[0]),
-        .req_port_o     (dcache_req_ports_o[0]),
-        // icache address translation requests
-        .icache_areq_i  (icache_areq_i),
-        .asid_to_be_flushed_i,
-        .vaddr_to_be_flushed_i,
-        .icache_areq_o  (icache_areq_o),
-        .pmpcfg_i,
-        .pmpaddr_i,
-        .*
-    );
-  end else if (MMU_PRESENT && (riscv::XLEN == 32)) begin : gen_mmu_sv32
-    cva6_mmu_sv32 #(
+  if (MMU_PRESENT) begin : gen_mmu
+
+    localparam HYP_EXT = 0;  //CVA6Cfg.CVA6ConfigHExtEn
+    localparam VPN_LEN = (riscv::XLEN == 64) ? (HYP_EXT ? 29 : 27) : 20;
+    localparam PT_LEVELS = (riscv::XLEN == 64) ? 3 : 2;
+    localparam int unsigned mmu_ASID_WIDTH[HYP_EXT:0] = {ASID_WIDTH};
+
+
+    cva6_mmu #(
         .CVA6Cfg          (CVA6Cfg),
         .INSTR_TLB_ENTRIES(ariane_pkg::INSTR_TLB_ENTRIES),
         .DATA_TLB_ENTRIES (ariane_pkg::DATA_TLB_ENTRIES),
-        .ASID_WIDTH       (ASID_WIDTH)
+        .HYP_EXT          (HYP_EXT),
+        .ASID_WIDTH       (mmu_ASID_WIDTH),
+        .VPN_LEN          (VPN_LEN),
+        .PT_LEVELS        (PT_LEVELS)
     ) i_cva6_mmu (
+        .clk_i                 (clk_i),
+        .rst_ni                (rst_ni),
+        .flush_i               (flush_i),
+        .enable_translation_i  ({enable_translation_i}),
+        .en_ld_st_translation_i({en_ld_st_translation_i}),
+        .icache_areq_i         (icache_areq_i),
+        .icache_areq_o         (icache_areq_o),
         // misaligned bypass
-        .misaligned_ex_i(misaligned_exception),
-        .lsu_is_store_i (st_translation_req),
-        .lsu_req_i      (translation_req),
-        .lsu_vaddr_i    (mmu_vaddr),
+        .misaligned_ex_i       (misaligned_exception),
+        .lsu_req_i             (translation_req),
+        .lsu_vaddr_i           (mmu_vaddr),
+        .lsu_tinst_i           (0),
+        .lsu_is_store_i        (st_translation_req),
+        .csr_hs_ld_st_inst_o   (),
+        .lsu_dtlb_hit_o        (dtlb_hit),                  // send in the same cycle as the request
+        .lsu_dtlb_ppn_o        (dtlb_ppn),                  // send in the same cycle as the request
+
         .lsu_valid_o    (translation_valid),
         .lsu_paddr_o    (mmu_paddr),
         .lsu_exception_o(mmu_exception),
-        .lsu_dtlb_hit_o (dtlb_hit),               // send in the same cycle as the request
-        .lsu_dtlb_ppn_o (dtlb_ppn),               // send in the same cycle as the request
-        // connecting PTW to D$ IF
-        .req_port_i     (dcache_req_ports_i[0]),
-        .req_port_o     (dcache_req_ports_o[0]),
-        // icache address translation requests
-        .icache_areq_i  (icache_areq_i),
-        .asid_to_be_flushed_i,
-        .vaddr_to_be_flushed_i,
-        .icache_areq_o  (icache_areq_o),
+
+        .priv_lvl_i      (priv_lvl_i),
+        .ld_st_priv_lvl_i(ld_st_priv_lvl_i),
+
+        .sum_i          ({sum_i}),
+        .mxr_i          ({mxr_i}),
+        .hlvx_inst_i    (0),
+        .hs_ld_st_inst_i(0),
+
+        .satp_ppn_i           ({satp_ppn_i}),
+        .asid_i               ({asid_i}),
+        .asid_to_be_flushed_i ({asid_to_be_flushed_i}),
+        .vaddr_to_be_flushed_i({vaddr_to_be_flushed_i}),
+        .flush_tlb_i          ({flush_tlb_i}),
+
+        .itlb_miss_o(itlb_miss_o),
+        .dtlb_miss_o(dtlb_miss_o),
+
+        .req_port_i(dcache_req_ports_i[0]),
+        .req_port_o(dcache_req_ports_o[0]),
         .pmpcfg_i,
-        .pmpaddr_i,
-        .*
+        .pmpaddr_i
     );
   end else begin : gen_no_mmu
 

core/mmu_unify/README.md

@@ -0,0 +1 @@
+Unification of MMUs: sv32, sv39 and sv39x4