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Zcmp extension support #1779

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rohan-10xe
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Zcmp Extension

Introduction

This PR is adding a set of instructions(cm.push, cm.pop, cm.popret, cm.popretz, cm.mvsa01, and cm.mva01s) that may be executed as a series of existing 32-bit RISC-V instructions. The objective is to reduce the overall code size for embedded platforms.

Adding Support in CVA6

Since the new set of instructions is executed as a series of existing 32-bit instructions we need a special sequential decoder that stalls the fetching of a new instruction until all the corresponding instructions are generated (one instruction in every cycle) and issued.

This new decoder extends the existing compressed decoder and the main decoder in the instruction decode stage.


Our new zcmp_decoder has the following important features:

  1. It has an input signal to indicate that the current instruction is a zcmp instruction and needs to be decoded into a series of 32-bit instructions. 

  2. It has an input signal from the Issue Stage indicating the last issued instruction has been acknowledged. So, we can decode and send the next instruction in the series.

  3. It has an output signal to indicate that the zcmp decoder is busy decoding the current instruction into a series of instructions and instruction fetching should be stalled as long as it is busy.

Design Changes

  1. compressed_decoder

Updated the compressed decoder to indicate that the current compressed instruction is of zcmp extension.

  1. id_stage

As mentioned we need to instantiate and connect our new zcmp_decoder between the compressed decoder and the main larger decoder when the zcmp extension is enabled in the cva6 configuration. Furthermore, we need to stall the fetching of new instructions until our zcmp_decoder is busy.


Test Plan 


Sr. No. Test Name Description Passing Criteria Status
1 C_test A simple program in C where we call a method to add two numbers and return true if the result is correct The program executes successfully with zcmp extension instructions in asm file Pending
2 Cm_push_pop_test A simple assembly program where cm.push and cm.pop is used instead of the push/pop instructions The program behaves the same way when used push/pop instructions Passing
3 Cm_popretz_test A simple assembly program where cm.popretz is used instead of the pop and ret instructions The program behaves the same way when used pop and ret instructions Passing
4 Cm_popret_test A simple assembly program where cm.popret is used instead of pop and ret instructions The program behaves the same way when used pop and ret instructions Passing
5 Cm_mvsa01_test A simple assembly program where cm.mvsa01 instruction is used instead of pairs of c.mv The program behaves the same way when used pairs of c.mv instructions Passing
6 Cm_mva01s_test A simple assembly program where cm.mva01s instruction is used instead of pairs of c.mv The program behaves the same way when used pairs of c.mv instructions Passing

Please find the tests under CVA6_REPO_DIR/verif/tests/custom/Zcmp/ along with the command to build the test binary file.


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❌ failed run, report available here.

Gchauvon pushed a commit to Gchauvon/cva6 that referenced this pull request Jan 24, 2024
cva6/docs/verif-approval: add file describing task approval process
@AyoubJalali
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Hi @arshadrohan5, there's an other PR for the Zcmp instruction for the Specification

@JeanRochCoulon
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Thanks @arshadrohan5 for this nice (and very wanted feature to reduce code size) contribution. Up to now the CO is failed. DO you have enough information to fix it ?

@rohan-10xe
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Thanks @arshadrohan5 for this nice (and very wanted feature to reduce code size) contribution. Up to now the CO is failed. DO you have enough information to fix it ?

No, I don't have enough information to fix it.

@JeanRochCoulon
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For of all, I would propose you to run the smoke-tests on your local env fllowing the README.md
This is based on cva6.py execution, the same command as what is used by Thales CI

Let me know

@ASintzoff
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As the push/pop instructions are transformed into a series of store/load instructions, what is the expected behaviour when an interruption occurs during the execution of the series of store/load instructions? Is the series interrupted? Is the whole series executed and the interruption handled afterwards?

Similar questions exist also when an exception occurs.

These behaviours should be described to know how to verify this extension.

@rohan-10xe rohan-10xe force-pushed the Zcmp_extension_support branch from 1038667 to 008bab6 Compare February 3, 2024 05:29
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github-actions bot commented Feb 3, 2024

❌ failed run, report available here.

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github-actions bot commented Feb 3, 2024

❌ failed run, report available here.

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github-actions bot commented Feb 3, 2024

❌ failed run, report available here.

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github-actions bot commented Feb 3, 2024

❌ failed run, report available here.

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github-actions bot commented Feb 3, 2024

❌ failed run, report available here.

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github-actions bot commented Feb 3, 2024

❌ failed run, report available here.

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github-actions bot commented Feb 3, 2024

❌ failed run, report available here.

@ASintzoff
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As the push/pop instructions are transformed into a series of instructions and as these instructions are going through the issue, the execute and the commit stages, minstret CSR will be incremented by more than one for push/pop instructions. From an architectural point of view, a Zcmp instruction is only one instruction, so minstret CSR shall be incremented only by one when a Zcmp instruction is retired.

@ASintzoff
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In the RVFI trace generated by the CVA6, each retired (committed) instruction has to be traced. With this current Zcmp implementation, the trace will contain multiple instructions (store/load, add) instead of one (push/pop).

Comment on lines 552 to 609
if (riscv::XLEN == 64) begin
if (issue_ack_i && is_zcmp_instr_i && zcmp_instr_type == PUSH) begin
// addi sp, sp, stack_adj
instr_o_reg = {itype_inst.imm, 5'h2, 3'h0, 5'h2, riscv::OpcodeOpImm};
end else begin
if (issue_ack_i) begin
instr_o_reg = {stack_adj, 5'h2, 3'h0, 5'h2, riscv::OpcodeOpImm};
end
end
if (issue_ack_i && is_zcmp_instr_i && (zcmp_instr_type == POPRETZ || zcmp_instr_type == POPRET)) begin
state_d = POPRETZ_1;
fetch_stall_o = 1;
end else begin
if (issue_ack_i) begin
state_d = IDLE;
fetch_stall_o = 0;
end else begin
fetch_stall_o = 1;
end
end
end else begin
if (issue_ack_i && is_zcmp_instr_i && zcmp_instr_type == PUSH) begin
// addi sp, sp, stack_adj
instr_o_reg = {itype_inst.imm, 5'h2, 3'h0, 5'h2, riscv::OpcodeOpImm};
end else begin
if (issue_ack_i) begin
instr_o_reg = {stack_adj, 5'h2, 3'h0, 5'h2, riscv::OpcodeOpImm};
end
end
if (issue_ack_i && is_zcmp_instr_i && (zcmp_instr_type == POPRETZ || zcmp_instr_type == POPRET)) begin
state_d = POPRETZ_1;
fetch_stall_o = 1;
end else begin
if (issue_ack_i) begin
state_d = IDLE;
fetch_stall_o = 0;
end else begin
fetch_stall_o = 1;
end
end
end
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It seems that the code for RV64 is the same as the one for RV32.

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@JeanRochCoulon
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Can you remove the "rename" file.
Can you replace "is_mv_macro_instr" by "is_double_rd_macro_instr" to be more generic.
Thanks

@@ -38,6 +38,8 @@ module commit_stage
input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
// Acknowledge that we are indeed committing - ISSUE_STAGE
output logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_o,
// Acknowledge that we are indeed committing - CSR_REGFILE
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why CSR_REGFILE and not ISSUE_STAGE as destination of commit_macro_ack_o?

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The goal was to increment the CSR register only once for a macro instruction. We still want to be able to Issue and Execute the decoded sequence of instructions. Please note here that commit_macro_ack_o is asserted only when we execute the last decoded 32bit instruction in the macro definition, otherwise it behaves exactly like commit_ack_o.

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❌ failed run, report available here.

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❌ failed run, report available here.

@JeanRochCoulon
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FYI the Dashboard service is down, I keep you in touch

@valentinThomazic
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The dashboard is up and running again, but the report for the fpga build job is "failed" due to a previous Gitlab Runner issue, I started the job again.

@ASintzoff
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It seems there is still formatting issues. See this.

I just take a look at the verilator build log. A few lint warnings are reported.

%Warning-WIDTHEXPAND: ../cva6/core/scoreboard.sv:191:32: Operator SUB expects 32 or 8 bits on the LHS, but LHS's SEL generates 2 bits.
                                                                                 : ... In instance ariane_testharness.i_ariane.i_cva6.issue_stage_i.i_scoreboard
  191 |             mem_n[trans_id_i[i]-1].sbe.valid = 1'b1;
      |                                ^
%Warning-WIDTHEXPAND: ../cva6/core/macro_decoder.sv:264:26: Operator NOT expects 12 bits on the LHS, but LHS's VARREF 'stack_adj' generates 9 bits.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  264 |         itype_inst.imm = ~stack_adj + 1'b1;
      |                          ^
%Warning-WIDTHEXPAND: ../cva6/core/macro_decoder.sv:266:36: Operator SUB expects 12 bits on the LHS, but LHS's VARREF 'stack_adj' generates 9 bits.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  266 |         itype_inst.imm = stack_adj - 3'b100;
      |                                    ^
%Warning-WIDTHEXPAND: ../cva6/core/macro_decoder.sv:266:36: Operator SUB expects 12 bits on the RHS, but RHS's CONST '3'h4' generates 3 bits.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  266 |         itype_inst.imm = stack_adj - 3'b100;
      |                                    ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:377:30: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  377 |                   offset_reg - 4, 5'h2, 3'h3, 5'h1, riscv::OpcodeLoad
      |                              ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:377:33: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  377 |                   offset_reg - 4, 5'h2, 3'h3, 5'h1, riscv::OpcodeLoad
      |                                 ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:377:39: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  377 |                   offset_reg - 4, 5'h2, 3'h3, 5'h1, riscv::OpcodeLoad
      |                                       ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:377:45: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  377 |                   offset_reg - 4, 5'h2, 3'h3, 5'h1, riscv::OpcodeLoad
      |                                             ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:377:51: Unsized numbers/parameters not allowed in replications.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  377 |                   offset_reg - 4, 5'h2, 3'h3, 5'h1, riscv::OpcodeLoad
      |                                                   ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:397:43: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  397 |                 instr_o_reg = {offset_reg - 4, 5'h2, 3'h3, 5'h8, riscv::OpcodeLoad};
      |                                           ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:397:46: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  397 |                 instr_o_reg = {offset_reg - 4, 5'h2, 3'h3, 5'h8, riscv::OpcodeLoad};
      |                                              ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:397:52: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  397 |                 instr_o_reg = {offset_reg - 4, 5'h2, 3'h3, 5'h8, riscv::OpcodeLoad};
      |                                                    ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:397:58: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  397 |                 instr_o_reg = {offset_reg - 4, 5'h2, 3'h3, 5'h8, riscv::OpcodeLoad};
      |                                                          ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:397:64: Unsized numbers/parameters not allowed in replications.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  397 |                 instr_o_reg = {offset_reg - 4, 5'h2, 3'h3, 5'h8, riscv::OpcodeLoad};
      |                                                                ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:405:43: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  405 |                 instr_o_reg = {offset_reg - 4, 5'h2, 3'h3, 5'h9, riscv::OpcodeLoad};
      |                                           ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:405:46: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  405 |                 instr_o_reg = {offset_reg - 4, 5'h2, 3'h3, 5'h9, riscv::OpcodeLoad};
      |                                              ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:405:52: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  405 |                 instr_o_reg = {offset_reg - 4, 5'h2, 3'h3, 5'h9, riscv::OpcodeLoad};
      |                                                    ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:405:58: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  405 |                 instr_o_reg = {offset_reg - 4, 5'h2, 3'h3, 5'h9, riscv::OpcodeLoad};
      |                                                          ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:405:64: Unsized numbers/parameters not allowed in replications.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  405 |                 instr_o_reg = {offset_reg - 4, 5'h2, 3'h3, 5'h9, riscv::OpcodeLoad};
      |                                                                ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:413:43: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  413 |                 instr_o_reg = {offset_reg - 4, 5'h2, 3'h3, store_reg, riscv::OpcodeLoad};
      |                                           ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:413:46: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  413 |                 instr_o_reg = {offset_reg - 4, 5'h2, 3'h3, store_reg, riscv::OpcodeLoad};
      |                                              ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:413:52: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  413 |                 instr_o_reg = {offset_reg - 4, 5'h2, 3'h3, store_reg, riscv::OpcodeLoad};
      |                                                    ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:413:58: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  413 |                 instr_o_reg = {offset_reg - 4, 5'h2, 3'h3, store_reg, riscv::OpcodeLoad};
      |                                                          ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:413:69: Unsized numbers/parameters not allowed in replications.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  413 |                 instr_o_reg = {offset_reg - 4, 5'h2, 3'h3, store_reg, riscv::OpcodeLoad};
      |                                                                     ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:606:43: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  606 |             instr_o_reg = {itype_inst.imm - 4, 5'h2, 3'h0, 5'h2, riscv::OpcodeOpImm};
      |                                           ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:606:46: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  606 |             instr_o_reg = {itype_inst.imm - 4, 5'h2, 3'h0, 5'h2, riscv::OpcodeOpImm};
      |                                              ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:606:52: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  606 |             instr_o_reg = {itype_inst.imm - 4, 5'h2, 3'h0, 5'h2, riscv::OpcodeOpImm};
      |                                                    ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:606:58: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  606 |             instr_o_reg = {itype_inst.imm - 4, 5'h2, 3'h0, 5'h2, riscv::OpcodeOpImm};
      |                                                          ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:606:64: Unsized numbers/parameters not allowed in replications.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  606 |             instr_o_reg = {itype_inst.imm - 4, 5'h2, 3'h0, 5'h2, riscv::OpcodeOpImm};
      |                                                                ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:609:40: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  609 |               instr_o_reg = {stack_adj - 4, 5'h2, 3'h0, 5'h2, riscv::OpcodeOpImm};
      |                                        ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:609:43: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  609 |               instr_o_reg = {stack_adj - 4, 5'h2, 3'h0, 5'h2, riscv::OpcodeOpImm};
      |                                           ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:609:49: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  609 |               instr_o_reg = {stack_adj - 4, 5'h2, 3'h0, 5'h2, riscv::OpcodeOpImm};
      |                                                 ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:609:55: Unsized numbers/parameters not allowed in concatenations.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  609 |               instr_o_reg = {stack_adj - 4, 5'h2, 3'h0, 5'h2, riscv::OpcodeOpImm};
      |                                                       ^
%Warning-WIDTHCONCAT: ../cva6/core/macro_decoder.sv:609:61: Unsized numbers/parameters not allowed in replications.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  609 |               instr_o_reg = {stack_adj - 4, 5'h2, 3'h0, 5'h2, riscv::OpcodeOpImm};
      |                                                             ^
%Warning-WIDTHEXPAND: ../cva6/core/macro_decoder.sv:630:27: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's REPLICATE generates 29 bits.
                                                                                    : ... In instance ariane_testharness.i_ariane.i_cva6.id_stage_i.genblk1.genblk1.macro_decoder_i
  630 |               instr_o_reg = {stack_adj, 5'h2, 3'h0, 5'h2, riscv::OpcodeOpImm};
      |                           ^

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❌ failed run, report available here.

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❌ failed run, report available here.

@rohan-10xe rohan-10xe force-pushed the Zcmp_extension_support branch from a273ea8 to 599253b Compare March 13, 2024 07:52
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❌ failed run, report available here.

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✔️ successful run, report available here.

@JeanRochCoulon
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Thanks for your patience, let's merge.

@JeanRochCoulon JeanRochCoulon merged commit c827c3b into openhwgroup:master Mar 13, 2024
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6 participants