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Break Timing Loop in Axi Adapter Arbiter of WB Cache #1761

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merged 1 commit into from
Jan 15, 2024
Merged

Break Timing Loop in Axi Adapter Arbiter of WB Cache #1761

merged 1 commit into from
Jan 15, 2024

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domenicw
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There exists a timing loop in the WB cache caused by the axi_adapter_arbiter module. This PR fixes it by breaking the connection between the rsp_i.gnt and rsp_o[sel_q].gnt signals. At the same time, this PR also removes an unnecessary cycle delay between two requests on the same port.

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✔️ successful run, report available here.

zarubaf
zarubaf approved these changes Jan 15, 2024
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Thanks @domenicw!

fyi @colluca @niwis

@zarubaf zarubaf merged commit 49cdc90 into openhwgroup:master Jan 15, 2024
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rohan-10xe pushed a commit to 10x-Engineers/cva6 that referenced this pull request Jan 23, 2024
@domenicw @rohan-10xe
Break timing loop in axi adapter arbiter of WB cache (openhwgroup#1761)
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@hhhsiang hhhsiang mentioned this pull request Oct 21, 2024
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@hhhsiang
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Hi @domenicw, when I synthesize cva6 core with WB cache, the timing loop is still exist. Do you encounter this? #2557

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@zarubaf zarubaf zarubaf approved these changes

@JeanRochCoulon JeanRochCoulon Awaiting requested review from JeanRochCoulon JeanRochCoulon is a code owner

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@domenicw @hhhsiang @zarubaf