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652 changes: 652 additions & 0 deletions AXI_Interface.rst
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102 changes: 102 additions & 0 deletions CSR_Performance_Counters.rst
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..
Copyright (c) 2023 OpenHW Group
Copyright (c) 2023 Thales DIS design services SAS

SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1

.. Level 1
=======

Level 2
-------

Level 3
~~~~~~~

Level 4
^^^^^^^

.. _cva6_csr_performance_counters:

*Applicability of this chapter to configurations:*

.. csv-table::
:widths: auto
:align: left
:header: "Configuration", "Implementation"

"CV32A60X", "Performance counters included"
"CV32A60MX", "No performance counters"

CSR performance counters control
================================
CVA6 implements performance counters according to the RISC-V Privileged Specification, version 1.11 (see Hardware Performance Monitor, Section 3.1.10). The performance counters are placed inside the Control and Status Registers(CSRs) and can be accessed with the ``CSRRW(I)`` and ``CSRRS/C(I)`` instructions.

CVA6 implements the standard 64-bit clock cycle counter ``mcycle``, the retired instruction counter ``minstret`` as well as the six generic 64-bit event counters ``mhpm_counter_3`` to ``mhpm_counter_8`` including their upper 32 bits counterparts ``mhpm_counter_3h`` to ``mhpm_counter_8h``. The corresponding event selectors ``mhpm_event_3`` to ``mhpm_event_8`` are implemented for the selection of the source of events. The unavailable counters (``mhpm_counter_9(h)`` to ``mhpm_counter_31(h)``) and event selector (``mhpm_event_9`` to ``mhpm_event_31``) always read 0.

The ``mcountinhibit`` CSR is used to individually inhibit the incrementing of the counters. The read-only shadows of the counters are also implemented as ``cycle``, ``instret`` and ``hpmcountern``. The ``mcycle`` and ``minstret`` counters are always available but the ``mhpmcounter`` are optional and can be configured through the parameter ``PERF_COUNTER_EN``. The supervisor and user access of performance counters are allowed through enabling of ``mcounteren`` and ``scounteren`` CSRs.

Event Selector
-------------------------------
The event selector CSRs ``mhpm_event_3`` to ``mhpm_event_8`` controls which of the events are counted by the six generic event counters ``mhpm_counter_3`` to ``mhpm_counter_8`` respectively.

The five least significant bit(LSB) of the event selector CSRs are written to select the event that one needs to count from a particular generic event counter. Thus, we can count six different events at a time using the six generic counters.

Each of the six generic performance counters is able to monitor events from one of these sources:

+----------+-----------------------------+---------------------------------------------------------------+
| Event ID | Event Name | Description |
+==========+=============================+===============================================================+
| 1 | L1 I-Cache Misses | Number of misses in L1 I-Cache |
+----------+-----------------------------+---------------------------------------------------------------+
| 2 | L1 D-Cache Misses | Number of misses in L1 D-Cache |
+----------+-----------------------------+---------------------------------------------------------------+
| 3 | ITLB Misses | Number of misses in ITLB |
+----------+-----------------------------+---------------------------------------------------------------+
| 4 | DTLB Misses | Number of misses in DTLB |
+----------+-----------------------------+---------------------------------------------------------------+
| 5 | Load Accesses | Number of data memory loads |
+----------+-----------------------------+---------------------------------------------------------------+
| 6 | Store Accesses | Number of data memory stores |
+----------+-----------------------------+---------------------------------------------------------------+
| 7 | Exceptions | Valid Exceptions encountered |
+----------+-----------------------------+---------------------------------------------------------------+
| 8 | Exception Handler Returns | Return from an exception |
+----------+-----------------------------+---------------------------------------------------------------+
| 9 | Branch Instructions | Number of branch instructions encountered |
+----------+-----------------------------+---------------------------------------------------------------+
| 10 | Branch Mispredicts | Number of branch mispredictions |
+----------+-----------------------------+---------------------------------------------------------------+
| 11 | Branch Exceptions | Number of valid branch exceptions |
+----------+-----------------------------+---------------------------------------------------------------+
| 12 | Call | Number of call instructions |
+----------+-----------------------------+---------------------------------------------------------------+
| 13 | Return | Number of return instructions |
+----------+-----------------------------+---------------------------------------------------------------+
| 14 | MSB Full | Scoreboard is full |
+----------+-----------------------------+---------------------------------------------------------------+
| 15 | Instruction Fetch Empty | Number of invalid instructions in IF |
+----------+-----------------------------+---------------------------------------------------------------+
| 16 | L1 I-Cache Accesses | Number of accesses to Instruction Cache |
+----------+-----------------------------+---------------------------------------------------------------+
| 17 | L1 D-Cache Accesses | Number of accesses to Data Cache |
+----------+-----------------------------+---------------------------------------------------------------+
| 18 | L1 Cache Line Eviction | Number of Data Cache line eviction |
+----------+-----------------------------+---------------------------------------------------------------+
| 19 | ITLB Flush | Number of ITLB Flushes |
+----------+-----------------------------+---------------------------------------------------------------+
| 20 | Integer Instructions | Number of Integer instructions |
+----------+-----------------------------+---------------------------------------------------------------+
| 21 | Floating Point Instructions | Number of Floating point instructions |
+----------+-----------------------------+---------------------------------------------------------------+
| 22 | Pipeline Stall | Number of cycles the pipeline is stalled during read operands |
+----------+-----------------------------+---------------------------------------------------------------+
| 23-31 | Reserved | Reserved |
+----------+-----------------------------+---------------------------------------------------------------+

Controlling the counters from software
---------------------------------------
All performance counters are enabled after reset. The ``mcountinhibit`` CSR at address ``0x320`` controls which of the performance counters increment as described in the RISC-V Privileged Specification, version 1.11 (see Machine Counter-Inhibit CSR, Section 3.1.12). For instance, bit 0 is set to 0 for ``mcycle(h)`` to increment as usual, bit 2 for ``minstrert(h)`` and bit X for event counter mhpmcounterX(h).

The lower 32 bits of all counters can be accessed through the base register, whereas the upper 32 bits are accessed through the h-register.

204 changes: 204 additions & 0 deletions CVX_Interface_Coprocessor.rst
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..
Copyright (c) 2023 OpenHW Group
Copyright (c) 2023 Thales

SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1

.. Level 1
=======

Level 2
-------

Level 3
~~~~~~~

Level 4
^^^^^^^

.. _cva6_cvx_interface_coprocessor:

CV-X-IF Interface and Coprocessor
=================================

The CV-X-IF interface of CVA6 allows to extend its supported instruction set
with external coprocessors.

*Applicability of this chapter to configurations:*

.. csv-table::
:widths: auto
:align: left
:header: "Configuration", "Implementation"

"CV32A60X", "CV-X-IF included"
"CV32A60MX", "CV-X-IF included"


CV-X-IF interface specification
-------------------------------

Description
~~~~~~~~~~~
This design specification presents global functionalities of
Core-V-eXtension-Interface (XIF, CVXIF, CV-X-IF, X-interface) in the CVA6 core.

.. code-block:: text

The CORE-V X-Interface is a RISC-V eXtension interface that provides a
generalized framework suitable to implement custom coprocessors and ISA
extensions for existing RISC-V processors.

--core-v-xif Readme, https://github.com/openhwgroup/core-v-xif

The specification of the CV-X-IF bus protocol can be found at [CV-X-IF].

CV-X-IF aims to:

* Create interfaces to connect a coprocessor to the CVA6 to execute instructions.
* Offload CVA6 illegal instrutions to the coprocessor to be executed.
* Get the results of offloaded instructions from the coprocessor so they are written back into the CVA6 register file.
* Add standard RISC-V instructions unsupported by CVA6 or custom instructions and implement them in a coprocessor.
* Kill offloaded instructions to allow speculative execution in the coprocessor. (Unsupported in CVA6 yet)
* Connect the coprocessor to memory via the CVA6 Load and Store Unit. (Unsupported in CVA6 yet)

The coprocessor operates like another functional unit so it is connected to
the CVA6 in the execute stage.

Only the 3 mandatory interfaces from the CV-X-IF specification (issue, commit and result
) have been implemented.
Compressed interface, Memory Interface and Memory result interface are not yet
implemented in the CVA6.

Supported Parameters
~~~~~~~~~~~~~~~~~~~~
The following table presents CVXIF parameters supported by CVA6.

=============== =========================== ===============================================
Signal Value Description
=============== =========================== ===============================================
**X_NUM_RS** int: 2 or 3 (configurable) | Number of register file read ports that can
| be used by the eXtension interface
**X_ID_WIDTH** int: 3 | Identification width for the eXtension
| interface
**X_MEM_WIDTH** n/a (feature not supported) | Memory access width for loads/stores via the
| eXtension interface
**X_RFR_WIDTH** int: ``XLEN`` (32 or 64) | Register file read access width for the
| eXtension interface
**X_RFW_WIDTH** int: ``XLEN`` (32 or 64) | Register file write access width for the
| eXtension interface
**X_MISA** logic[31:0]: 0x0000_0000 | MISA extensions implemented on the eXtension
| interface
=============== =========================== ===============================================

CV-X-IF Enabling
~~~~~~~~~~~~~~~~
CV-X-IF can be enabled or disabled via the ``CVA6ConfigCvxifEn`` parameter in the SystemVerilog source code.

Illegal instruction decoding
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The CVA6 decoder module detects illegal instructions for the CVA6, prepares exception field
with relevant information (exception code "ILLEGAL INSTRUCTION", instruction value).

The exception valid flag is raised in CVA6 decoder when CV-X-IF is disabled. Otherwise
it is not raised at this stage because the decision belongs to the coprocessor
after the offload process.

RS3 support
~~~~~~~~~~~
The number of source registers used by the CV-X-IF coprocessor is configurable with 2 or
3 source registers.

If CV-X-IF is enabled and configured with 3 source registers,
a third read port is added to the CVA6 general purpose register file.

Description of interface connections between CVA6 and Coprocessor
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In CVA6 execute stage, there is a new functional unit dedicated to drive the CV-X-IF interfaces.
Here is *how* and *to what* CV-X-IF interfaces are connected to the CVA6.

* Issue interface
- Request
+ | Operands are connected to ``issue_req.rs`` signals
+ | Scoreboard transaction id is connected to ``issue_req.id`` signal.
| Therefore scoreboard ids and offloaded instruction ids are linked
| together (equal in this implementation). It allows the CVA6 to do out
| of order execution with the coprocessor in the same way as other
| functional units.
+ | Undecoded instruction is connected to ``issue_req.instruction``
+ | Valid signal for CVXIF functional unit is connected to
| ``issue_req.valid``
+ | All ``issue_req.rs_valid`` signals are set to 1. The validity of source
| registers is assured by the validity of valid signal sent from issue stage.
- Response
+ | If ``issue_resp.accept`` is set during a transaction (i.e. issue valid
| and ready are set), the offloaded instruction is accepted by the coprocessor
| and a result transaction will happen.
+ | If ``issue_resp.accept`` is not set during a transaction, the offloaded
| instruction is illegal and an illegal instruction exception will be
| raised as soon as no result transaction are written on the writeback bus.

* Commit interface
- | Valid signal of commit interface is connected to the valid signal of
| issue interface.
- | Id signal of commit interface is connected to issue interface id signal
| (i.e. scoreboard id).
- | Killing of offload instruction is never set. (Unsupported feature)
- | Therefore all accepted offloaded instructions are commited to their
| execution and no killing of instruction is possible in this implementation.

* Result interface
- Request
+ | Ready signal of result interface is always set as CVA6 is always ready
| to take a result from coprocessor for an accepted offloaded instruction.
- Response
+ | Result response is directly connected to writeback bus of the CV-X-IF
| functionnal unit.
+ | Valid signal of result interface is connected to valid signal of
| writeback bus.
+ | Id signal of result interface is connected to scoreboard id of
| writeback bus.
+ | Write enable signal of result interface is connected to a dedicated CV-X-IF WE
| signal in CVA6 which signals scoreboard if a writeback should happen
| or not to the CVA6 register file.
+ | ``exccode`` and ``exc`` signal of result interface are connected to exception
| signals of writeback bus. Exception from coprocessor does not write
| the ``tval`` field in exception signal of writeback bus.
+ | Three registers are added to hold illegal instruction information in
| case a result transaction and a non-accepted issue transaction happen
| in the same cycle. Result transactions will be written to the writeback
| bus in this case having priority over the non-accepted instruction due
| to being linked to an older offloaded instruction. Once the writeback
| bus is free, an illegal instruction exception will be raised thanks to
| information held in these three registers.

Coprocessor recommendations for use with CVA6's CV-X-IF
-------------------------------------------------------

CVA6 supports all coprocessors supporting the CV-X-IF specification with the exception of :

* Coprocessor requiring the Memory interface and Memory result interface (not implemented in CVA6 yet).
- All memory transaction should happen via the Issue interface, i.e. Load into CVA6 register file
then initialize an issue transaction.
* Coprocessor requiring the Compressed interface (not implemented in CVA6 yet).
- RISC-V Compressed extension (RVC) is already implemented in CVA6. User Space for custom compressed instruction
is not big enough to have RVC and a custom compressed extension.
* Stateful coprocessors.
- CVA6 will commit on the Commit interface all its issue transactions. Speculation
informations are only kept in the CVA6 and speculation process is only done in CVA6.
The coprocessor shall be stateless otherwise it will not be able to revert its state if CVA6 kills an
in-flight instruction (in case of mispredict or flush).

How to use CVA6 without CV-X-IF interface
-----------------------------------------
Select a configuration with ``CVA6ConfigCvxifEn`` parameter disabled or change it for your configuration.

Never let the CV-X-IF interface unconnected with the ``CVA6ConfigCvxifEn`` parameter enabled.

How to design a coprocessor for the CV-X-IF interface
-----------------------------------------------------
*The team is looking for a contributor to write this section.*

How to program a CV-X-IF coprocessor
------------------------------------
*The team is looking for a contributor to write this section.*
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