Code coverage: condition RTL With parameters

core/axi_shim.sv

@@ -136,8 +136,18 @@ module axi_shim #(
           axi_req_o.aw_valid = 1'b1;
           axi_req_o.w_valid  = 1'b1;
 
-          // its a single write
-          if (wr_single_req) begin
+          if (CVA6Cfg.AxiBurstWriteEn && !wr_single_req) begin
+            wr_cnt_en = axi_resp_i.w_ready;
+
+            case ({
+              axi_resp_i.aw_ready, axi_resp_i.w_ready
+            })
+              2'b11:   wr_state_d = WAIT_LAST_W_READY;
+              2'b01:   wr_state_d = WAIT_LAST_W_READY_AW_READY;
+              2'b10:   wr_state_d = WAIT_LAST_W_READY;
+              default: ;
+            endcase
+          end else if (wr_single_req) begin  // its a single write
             wr_cnt_clr = 1'b1;
             // single req can be granted here
             wr_gnt_o   = axi_resp_i.aw_ready & axi_resp_i.w_ready;
@@ -149,17 +159,6 @@ module axi_shim #(
               default: wr_state_d = IDLE;
             endcase
             // its a request for the whole cache line
-          end else if (CVA6Cfg.AxiBurstWriteEn) begin
-            wr_cnt_en = axi_resp_i.w_ready;
-
-            case ({
-              axi_resp_i.aw_ready, axi_resp_i.w_ready
-            })
-              2'b11:   wr_state_d = WAIT_LAST_W_READY;
-              2'b01:   wr_state_d = WAIT_LAST_W_READY_AW_READY;
-              2'b10:   wr_state_d = WAIT_LAST_W_READY;
-              default: ;
-            endcase
           end
         end
       end
@@ -178,15 +177,14 @@ module axi_shim #(
       WAIT_LAST_W_READY: begin
         axi_req_o.w_valid = 1'b1;
 
-        // this is the last write
-        if (wr_cnt_done) begin
+        if (CVA6Cfg.AxiBurstWriteEn && axi_resp_i.w_ready && !wr_cnt_done) begin
+          wr_cnt_en = 1'b1;
+        end else if (wr_cnt_done) begin  // this is the last write
           if (axi_resp_i.w_ready) begin
             wr_state_d = IDLE;
             wr_cnt_clr = 1'b1;
             wr_gnt_o   = 1'b1;
           end
-        end else if (CVA6Cfg.AxiBurstWriteEn && axi_resp_i.w_ready) begin
-          wr_cnt_en = 1'b1;
         end
       end
       ///////////////////////////////////

core/csr_regfile.sv

@@ -1347,12 +1347,12 @@ module csr_regfile
       // check counter-enabled counter CSR accesses
       // counter address range is C00 to C1F
       if (csr_addr_i inside {[riscv::CSR_CYCLE : riscv::CSR_HPM_COUNTER_31]}) begin
-        if (priv_lvl_o == riscv::PRIV_LVL_M) begin
-          privilege_violation = 1'b0;
-        end else if (priv_lvl_o == riscv::PRIV_LVL_S && CVA6Cfg.RVS) begin
+        if (priv_lvl_o == riscv::PRIV_LVL_S && CVA6Cfg.RVS) begin
           privilege_violation = ~mcounteren_q[csr_addr_i[4:0]];
         end else if (priv_lvl_o == riscv::PRIV_LVL_U && CVA6Cfg.RVU) begin
           privilege_violation = ~mcounteren_q[csr_addr_i[4:0]] | ~scounteren_q[csr_addr_i[4:0]];
+        end else if (priv_lvl_o == riscv::PRIV_LVL_M) begin
+          privilege_violation = 1'b0;
         end
       end
     end

core/decoder.sv

@@ -1323,12 +1323,12 @@ module decoder
         // this exception is valid
         instruction_o.ex.valid = 1'b1;
         // depending on the privilege mode, set the appropriate cause
-        if (priv_lvl_i == riscv::PRIV_LVL_M) begin
-          instruction_o.ex.cause = riscv::ENV_CALL_MMODE;
-        end else if (priv_lvl_i == riscv::PRIV_LVL_S && CVA6Cfg.RVS) begin
+        if (priv_lvl_i == riscv::PRIV_LVL_S && CVA6Cfg.RVS) begin
           instruction_o.ex.cause = riscv::ENV_CALL_SMODE;
         end else if (priv_lvl_i == riscv::PRIV_LVL_U && CVA6Cfg.RVU) begin
           instruction_o.ex.cause = riscv::ENV_CALL_UMODE;
+        end else if (priv_lvl_i == riscv::PRIV_LVL_M) begin
+          instruction_o.ex.cause = riscv::ENV_CALL_MMODE;
         end
       end else if (ebreak) begin
         // this exception is valid

core/frontend/bht.sv

@@ -74,7 +74,7 @@ module bht #(
       bht_d = bht_q;
       saturation_counter = bht_q[update_pc][update_row_index].saturation_counter;
 
-      if (bht_update_i.valid && !debug_mode_i) begin
+      if ((bht_update_i.valid && CVA6Cfg.DebugEn && !debug_mode_i) || (bht_update_i.valid && !CVA6Cfg.DebugEn)) begin
         bht_d[update_pc][update_row_index].valid = 1'b1;
 
         if (saturation_counter == 2'b11) begin

core/frontend/frontend.sv

@@ -197,7 +197,7 @@ module frontend
         4'b0001: begin
           ras_pop  = 1'b0;
           ras_push = 1'b0;
-          if (btb_prediction_shifted[i].valid) begin
+          if (CVA6Cfg.BTBEntries && btb_prediction_shifted[i].valid) begin
             predict_address = btb_prediction_shifted[i].target_address;
             cf_type[i] = ariane_pkg::JumpR;
           end
@@ -390,7 +390,7 @@ module frontend
         icache_data_q  <= icache_data;
         icache_vaddr_q <= icache_dreq_i.vaddr;
         // Map the only three exceptions which can occur in the frontend to a two bit enum
-        if (icache_dreq_i.ex.cause == riscv::INSTR_PAGE_FAULT) begin
+        if (ariane_pkg::MMU_PRESENT && icache_dreq_i.ex.cause == riscv::INSTR_PAGE_FAULT) begin
           icache_ex_valid_q <= ariane_pkg::FE_INSTR_PAGE_FAULT;
         end else if (icache_dreq_i.ex.cause == riscv::INSTR_ACCESS_FAULT) begin
           icache_ex_valid_q <= ariane_pkg::FE_INSTR_ACCESS_FAULT;

core/issue_read_operands.sv

@@ -260,7 +260,7 @@ module issue_read_operands
       operand_b_n = rs2_i;
     end
 
-    if (forward_rs3) begin
+    if (CVA6Cfg.FpPresent && forward_rs3) begin
       imm_n = imm_forward_rs3;
     end
 

core/load_unit.sv

@@ -257,28 +257,6 @@ module load_unit
         end
       end
 
-      // Wait until the write-back buffer is empty in the data cache.
-      WAIT_WB_EMPTY: begin
-        // the write buffer is empty, so lets go and re-do the translation.
-        if (CVA6Cfg.NonIdemPotenceEn && dcache_wbuffer_not_ni_i) state_d = WAIT_TRANSLATION;
-      end
-
-      WAIT_TRANSLATION: begin
-        if (ariane_pkg::MMU_PRESENT || CVA6Cfg.NonIdemPotenceEn) begin
-          translation_req_o = 1'b1;
-          // we've got a hit and we can continue with the request process
-          if (dtlb_hit_i) state_d = WAIT_GNT;
-
-          // we got an exception
-          if (ex_i.valid) begin
-            // the next state will be the idle state
-            state_d  = IDLE;
-            // pop load - but only if we are not getting an rvalid in here - otherwise we will over-write an incoming transaction
-            pop_ld_o = ~req_port_i.data_rvalid;
-          end
-        end
-      end
-
       WAIT_GNT: begin
         // keep the translation request up
         translation_req_o   = 1'b1;
@@ -371,6 +349,22 @@ module load_unit
           req_port_o.tag_valid = 1'b1;
           // re-do the request
           state_d = WAIT_WB_EMPTY;
+        end else if (state_q == WAIT_WB_EMPTY && CVA6Cfg.NonIdemPotenceEn && dcache_wbuffer_not_ni_i) begin
+          // Wait until the write-back buffer is empty in the data cache.
+          // the write buffer is empty, so lets go and re-do the translation.
+          state_d = WAIT_TRANSLATION;
+        end else if(state_q == WAIT_TRANSLATION && (ariane_pkg::MMU_PRESENT || CVA6Cfg.NonIdemPotenceEn)) begin
+          translation_req_o = 1'b1;
+          // we've got a hit and we can continue with the request process
+          if (dtlb_hit_i) state_d = WAIT_GNT;
+
+          // we got an exception
+          if (ex_i.valid) begin
+            // the next state will be the idle state
+            state_d  = IDLE;
+            // pop load - but only if we are not getting an rvalid in here - otherwise we will over-write an incoming transaction
+            pop_ld_o = ~req_port_i.data_rvalid;
+          end
         end else begin
           state_d = IDLE;
         end

core/mult.sv

@@ -89,7 +89,7 @@ module mult
     // we've go a new division operation
     if (mult_valid_i && fu_data_i.operation inside {DIV, DIVU, DIVW, DIVUW, REM, REMU, REMW, REMUW}) begin
       // is this a word operation?
-      if (riscv::IS_XLEN64 && (fu_data_i.operation inside {DIVW, DIVUW, REMW, REMUW})) begin
+      if (riscv::IS_XLEN64 && (fu_data_i.operation == DIVW || fu_data_i.operation == DIVUW || fu_data_i.operation == REMW || fu_data_i.operation == REMUW)) begin
         // yes so check if we should sign extend this is only done for a signed operation
         if (div_signed) begin
           operand_a = sext32(fu_data_i.operand_a[31:0]);

core/scoreboard.sv

@@ -185,7 +185,7 @@ module scoreboard #(
         // write the exception back if it is valid
         if (ex_i[i].valid) mem_n[trans_id_i[i]].sbe.ex = ex_i[i];
         // write the fflags back from the FPU (exception valid is never set), leave tval intact
-        else if(CVA6Cfg.FpPresent && mem_q[trans_id_i[i]].sbe.fu inside {ariane_pkg::FPU, ariane_pkg::FPU_VEC}) begin
+        else if(CVA6Cfg.FpPresent && (mem_q[trans_id_i[i]].sbe.fu == ariane_pkg::FPU || mem_q[trans_id_i[i]].sbe.fu == ariane_pkg::FPU_VEC)) begin
           mem_n[trans_id_i[i]].sbe.ex.cause = ex_i[i].cause;
         end
       end

core/store_unit.sv

@@ -120,7 +120,7 @@ module store_unit
         st_valid_without_flush = 1'b1;
 
         // we have another request and its not an AMO (the AMO buffer only has depth 1)
-        if (valid_i && !instr_is_amo) begin
+        if ((valid_i && CVA6Cfg.RVA &&!instr_is_amo) || (valid_i && !CVA6Cfg.RVA)) begin
 
           translation_req_o = 1'b1;
           state_d = VALID_STORE;