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Verilator Tandem Support #1702

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Dec 12, 2023
Merged

Verilator Tandem Support #1702

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19 changes: 1 addition & 18 deletions .gitlab-ci.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -129,28 +129,11 @@ smoke:
DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge most architectures with most testbenchs configurations"
DASHBOARD_SORT_INDEX: 0
DASHBOARD_JOB_CATEGORY: "Basic"
parallel:
matrix:
- DV_SIMULATORS:
- "veri-testharness,spike"
- "vcs-testharness,spike"
- "vcs-uvm,spike"
script:
- source verif/regress/smoke-tests.sh
- !reference [.simu_after_script]

smoke-tandem:
extends:
- .fe_smoke_test
variables:
DASHBOARD_JOB_TITLE: "Smoke test $DV_SIMULATORS with tandem"
DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge most architectures with most testbenchs configurations"
DASHBOARD_SORT_INDEX: 0
DASHBOARD_JOB_CATEGORY: "Basic"
SPIKE_TANDEM: 1
parallel:
matrix:
- DV_SIMULATORS:
- "veri-testharness,spike"
- "vcs-testharness,spike"
- "vcs-uvm,spike"
script:
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6 changes: 3 additions & 3 deletions Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -541,7 +541,7 @@ xrun-check-benchmarks:
xrun-ci: xrun-asm-tests xrun-amo-tests xrun-mul-tests xrun-fp-tests xrun-benchmarks

# verilator-specific
verilate_command := $(verilator) --no-timing verilator_config.vlt \
verilate_command := $(verilator) --no-timing verilator_config.vlt \
-f core/Flist.cva6 \
$(filter-out %.vhd, $(ariane_pkg)) \
$(filter-out core/fpu_wrap.sv, $(filter-out %.vhd, $(filter-out %_config_pkg.sv, $(src)))) \
Expand All @@ -567,9 +567,9 @@ verilate_command := $(verilator) --no-timing verilator_config.vlt
$(if $(TRACE_COMPACT), --trace-fst $(VL_INC_DIR)/verilated_fst_c.cpp) \
$(if $(TRACE_FAST), --trace $(VL_INC_DIR)/verilated_vcd_c.cpp) \
-LDFLAGS "-L$(RISCV)/lib -L$(SPIKE_INSTALL_DIR)/lib -Wl,-rpath,$(RISCV)/lib -Wl,-rpath,$(SPIKE_INSTALL_DIR)/lib -lfesvr -lriscv $(if $(PROFILE), -g -pg,) -lpthread $(if $(TRACE_COMPACT), -lz,)" \
-CFLAGS "$(CFLAGS)$(if $(PROFILE), -g -pg,) -DVL_DEBUG" \
-CFLAGS "$(CFLAGS)$(if $(PROFILE), -g -pg,) -DVL_DEBUG -I$(SPIKE_INSTALL_DIR)" \
$(if $(SPIKE_TANDEM), +define+SPIKE_TANDEM, ) \
--cc --vpi \
--cc --vpi \
$(list_incdir) --top-module ariane_testharness \
--threads-dpi none \
--Mdir $(ver-library) -O3 \
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50 changes: 24 additions & 26 deletions corev_apu/tb/common/spike.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,6 @@
import ariane_pkg::*;
import rvfi_pkg::*;

import "DPI-C" function void spike_step(inout st_rvfi rvfi);

module spike #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg,
parameter type rvfi_instr_t = struct packed {
Expand Down Expand Up @@ -59,7 +57,7 @@ module spike #(
rvfi_initialize_spike('h1);
end

st_rvfi t_core, t_reference_model;
st_rvfi s_core, s_reference_model;
logic [63:0] pc64;
logic [31:0] rtl_instr;
logic [31:0] spike_instr;
Expand All @@ -71,30 +69,30 @@ module spike #(
for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin

if (rvfi_i[i].valid || rvfi_i[i].trap) begin
spike_step(t_reference_model);
t_core.order = rvfi_i[i].order;
t_core.insn = rvfi_i[i].insn;
t_core.trap = rvfi_i[i].trap;
t_core.cause = rvfi_i[i].cause;
t_core.halt = rvfi_i[i].halt;
t_core.intr = rvfi_i[i].intr;
t_core.mode = rvfi_i[i].mode;
t_core.ixl = rvfi_i[i].ixl;
t_core.rs1_addr = rvfi_i[i].rs1_addr;
t_core.rs2_addr = rvfi_i[i].rs2_addr;
t_core.rs1_rdata = rvfi_i[i].rs1_rdata;
t_core.rs2_rdata = rvfi_i[i].rs2_rdata;
t_core.rd1_addr = rvfi_i[i].rd_addr;
t_core.rd1_wdata = rvfi_i[i].rd_wdata;
t_core.pc_rdata = rvfi_i[i].pc_rdata;
t_core.pc_wdata = rvfi_i[i].pc_wdata;
t_core.mem_addr = rvfi_i[i].mem_addr;
t_core.mem_rmask = rvfi_i[i].mem_rmask;
t_core.mem_wmask = rvfi_i[i].mem_wmask;
t_core.mem_rdata = rvfi_i[i].mem_rdata;
t_core.mem_wdata = rvfi_i[i].mem_wdata;
s_core.order = rvfi_i[i].order;
s_core.insn = rvfi_i[i].insn;
s_core.trap = rvfi_i[i].trap;
s_core.cause = rvfi_i[i].cause;
s_core.halt = rvfi_i[i].halt;
s_core.intr = rvfi_i[i].intr;
s_core.mode = rvfi_i[i].mode;
s_core.ixl = rvfi_i[i].ixl;
s_core.rs1_addr = rvfi_i[i].rs1_addr;
s_core.rs2_addr = rvfi_i[i].rs2_addr;
s_core.rs1_rdata = rvfi_i[i].rs1_rdata;
s_core.rs2_rdata = rvfi_i[i].rs2_rdata;
s_core.rd1_addr = rvfi_i[i].rd_addr;
s_core.rd1_wdata = rvfi_i[i].rd_wdata;
s_core.pc_rdata = rvfi_i[i].pc_rdata;
s_core.pc_wdata = rvfi_i[i].pc_wdata;
s_core.mem_addr = rvfi_i[i].mem_addr;
s_core.mem_rmask = rvfi_i[i].mem_rmask;
s_core.mem_wmask = rvfi_i[i].mem_wmask;
s_core.mem_rdata = rvfi_i[i].mem_rdata;
s_core.mem_wdata = rvfi_i[i].mem_wdata;

rvfi_compare(t_core, t_reference_model);
rvfi_spike_step(s_core, s_reference_model);
rvfi_compare(s_core, s_reference_model);
end
end
end
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2 changes: 1 addition & 1 deletion verif/core-v-verif
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Submodule core-v-verif updated 13 files
+3 −2 lib/uvm_agents/uvma_rvfi/uvma_rvfi_constants.sv
+15 −8 lib/uvm_agents/uvma_rvfi/uvma_rvfi_tdefs.sv
+25 −6 lib/uvm_agents/uvma_rvfi/uvma_rvfi_utils.sv
+5 −4 lib/uvm_components/uvmc_rvfi_reference_model/uvmc_rvfi_spike.sv
+2 −1 vendor/riscv/riscv-isa-sim/Makefile.in
+7 −5 vendor/riscv/riscv-isa-sim/riscv/Proc.cc
+2 −1 vendor/riscv/riscv-isa-sim/riscv/Proc.h
+24 −14 vendor/riscv/riscv-isa-sim/riscv/Simulation.cc
+1 −1 vendor/riscv/riscv-isa-sim/riscv/Simulation.h
+9 −8 vendor/riscv/riscv-isa-sim/riscv/Types.h
+6 −3 vendor/riscv/riscv-isa-sim/riscv/dts.cc
+37 −4 vendor/riscv/riscv-isa-sim/riscv/riscv_dpi.cc
+8 −0 vendor/riscv/riscv-isa-sim/spike_main/spike.cc
11 changes: 9 additions & 2 deletions verif/tb/core/rvfi_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -4,9 +4,16 @@
// Pre-processor macros
`ifdef VERILATOR
`define uvm_info(TOP,MSG,LVL) \
$display(TOP + ":" + MSG);
begin \
string tmp = MSG; \
$display($sformatf("UVM_INFO @ %t ns : %s %s", $time, TOP ,tmp)); \
end

`define uvm_fatal(TOP,MSG) \
$display(TOP + ":" + MSG); $finish();
begin \
string tmp = MSG; \
$display($sformatf("UVM_FATAL @ %t ns : %s %s", $time, TOP ,tmp)); $finish(); \
end
`else
`include "uvm_macros.svh"
`endif
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