Code_coverage: condition RTL with the U-MODE parameter

core/csr_regfile.sv

@@ -163,7 +163,7 @@ module csr_regfile
   | (riscv::XLEN'(1) << 12)  // M - Integer Multiply/Divide extension
   | (riscv::XLEN'(0) << 13)  // N - User level interrupts supported
   | (riscv::XLEN'(CVA6Cfg.RVS) << 18)  // S - Supervisor mode implemented
-  | (riscv::XLEN'(1) << 20)  // U - User mode implemented
+  | (riscv::XLEN'(CVA6Cfg.RVU) << 20)  // U - User mode implemented
   | (riscv::XLEN'(CVA6Cfg.RVV) << 21)  // V - Vector extension
   | (riscv::XLEN'(CVA6Cfg.NSX) << 23)  // X - Non-standard extensions present
   | ((riscv::XLEN == 64 ? 2 : 1) << riscv::XLEN - 2);  // MXL
@@ -1139,8 +1139,10 @@ module csr_regfile
             end
           end
           riscv::PRIV_LVL_U: begin
-            debug_mode_d   = dcsr_q.ebreaku;
-            set_debug_pc_o = dcsr_q.ebreaku;
+            if (CVA6Cfg.RVU) begin
+              debug_mode_d   = dcsr_q.ebreaku;
+              set_debug_pc_o = dcsr_q.ebreaku;
+            end
           end
           default: ;
         endcase
@@ -1330,7 +1332,8 @@ module csr_regfile
           riscv::PRIV_LVL_M: privilege_violation = 1'b0;
           riscv::PRIV_LVL_S: if (CVA6Cfg.RVS) privilege_violation = ~mcounteren_q[csr_addr_i[4:0]];
           riscv::PRIV_LVL_U:
-          privilege_violation = ~mcounteren_q[csr_addr_i[4:0]] & ~scounteren_q[csr_addr_i[4:0]];
+          if (CVA6Cfg.RVU)
+            privilege_violation = ~mcounteren_q[csr_addr_i[4:0]] & ~scounteren_q[csr_addr_i[4:0]];
         endcase
       end
     end

core/cva6.sv

@@ -195,6 +195,7 @@ module cva6
     unsigned'(NrWbPorts),
     bit'(EnableAccelerator),
     CVA6Cfg.RVS,
+    CVA6Cfg.RVU,
     CVA6Cfg.HaltAddress,
     CVA6Cfg.ExceptionAddress,
     CVA6Cfg.RASDepth,

core/decoder.sv

@@ -147,7 +147,7 @@ module decoder
                     instruction_o.op = ariane_pkg::SRET;
                     // check privilege level, SRET can only be executed in S and M mode
                     // we'll just decode an illegal instruction if we are in the wrong privilege level
-                    if (priv_lvl_i == riscv::PRIV_LVL_U) begin
+                    if (CVA6Cfg.RVU && priv_lvl_i == riscv::PRIV_LVL_U) begin
                       illegal_instr = 1'b1;
                       //  do not change privilege level if this is an illegal instruction
                       instruction_o.op = ariane_pkg::ADD;
@@ -165,7 +165,7 @@ module decoder
                   instruction_o.op = ariane_pkg::MRET;
                   // check privilege level, MRET can only be executed in M mode
                   // otherwise we decode an illegal instruction
-                  if ((CVA6Cfg.RVS && priv_lvl_i == riscv::PRIV_LVL_S) || priv_lvl_i == riscv::PRIV_LVL_U)
+                  if ((CVA6Cfg.RVS && priv_lvl_i == riscv::PRIV_LVL_S) || (CVA6Cfg.RVU && priv_lvl_i == riscv::PRIV_LVL_U))
                     illegal_instr = 1'b1;
                 end
                 // DRET
@@ -184,7 +184,7 @@ module decoder
                     instruction_o.op = ariane_pkg::ADD;
                   end
                   // we don't support U mode interrupts so WFI is illegal in this context
-                  if (priv_lvl_i == riscv::PRIV_LVL_U) begin
+                  if (CVA6Cfg.RVU && priv_lvl_i == riscv::PRIV_LVL_U) begin
                     illegal_instr = 1'b1;
                     instruction_o.op = ariane_pkg::ADD;
                   end
@@ -1321,7 +1321,7 @@ module decoder
         case (priv_lvl_i)
           riscv::PRIV_LVL_M: instruction_o.ex.cause = riscv::ENV_CALL_MMODE;
           riscv::PRIV_LVL_S: if (CVA6Cfg.RVS) instruction_o.ex.cause = riscv::ENV_CALL_SMODE;
-          riscv::PRIV_LVL_U: instruction_o.ex.cause = riscv::ENV_CALL_UMODE;
+          riscv::PRIV_LVL_U: if (CVA6Cfg.RVU) instruction_o.ex.cause = riscv::ENV_CALL_UMODE;
           default: ;  // this should not happen
         endcase
       end else if (ebreak) begin
@@ -1393,7 +1393,7 @@ module decoder
         // mode equals the delegated privilege mode (S or U) and that mode’s interrupt enable bit
         // (SIE or UIE in mstatus) is set, or if the current privilege mode is less than the delegated privilege mode.
         if (irq_ctrl_i.mideleg[interrupt_cause[$clog2(riscv::XLEN)-1:0]]) begin
-          if ((CVA6Cfg.RVS && irq_ctrl_i.sie && priv_lvl_i == riscv::PRIV_LVL_S) || priv_lvl_i == riscv::PRIV_LVL_U) begin
+          if ((CVA6Cfg.RVS && irq_ctrl_i.sie && priv_lvl_i == riscv::PRIV_LVL_S) || (CVA6Cfg.RVU && priv_lvl_i == riscv::PRIV_LVL_U)) begin
             instruction_o.ex.valid = 1'b1;
             instruction_o.ex.cause = interrupt_cause;
           end

core/include/config_pkg.sv

@@ -72,6 +72,7 @@ package config_pkg;
     int unsigned                 NrWbPorts;
     bit                          EnableAccelerator;
     bit                          RVS;    //Supervisor mode
+    bit                          RVU;    //User mode
     // Debug Module
     // address to which a hart should jump when it was requested to halt
     logic [63:0]                 HaltAddress;

core/include/cv32a60x_config_pkg.sv

@@ -107,6 +107,7 @@ package cva6_config_pkg;
       NrWbPorts: unsigned'(0),
       EnableAccelerator: bit'(0),
       RVS: bit'(1),
+      RVU: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),

core/include/cv32a6_embedded_config_pkg.sv

@@ -106,6 +106,7 @@ package cva6_config_pkg;
       NrWbPorts: unsigned'(0),
       EnableAccelerator: bit'(0),
       RVS: bit'(0),
+      RVU: bit'(0),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),

core/include/cv32a6_ima_sv32_fpga_config_pkg.sv

@@ -107,6 +107,7 @@ package cva6_config_pkg;
       NrWbPorts: unsigned'(0),
       EnableAccelerator: bit'(0),
       RVS: bit'(1),
+      RVU: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),

core/include/cv32a6_imac_sv0_config_pkg.sv

@@ -107,6 +107,7 @@ package cva6_config_pkg;
       NrWbPorts: unsigned'(0),
       EnableAccelerator: bit'(0),
       RVS: bit'(1),
+      RVU: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),

core/include/cv32a6_imac_sv32_config_pkg.sv

@@ -107,6 +107,7 @@ package cva6_config_pkg;
       NrWbPorts: unsigned'(0),
       EnableAccelerator: bit'(0),
       RVS: bit'(1),
+      RVU: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),

core/include/cv32a6_imafc_sv32_config_pkg.sv

@@ -107,6 +107,7 @@ package cva6_config_pkg;
       NrWbPorts: unsigned'(0),
       EnableAccelerator: bit'(0),
       RVS: bit'(1),
+      RVU: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),

core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv

@@ -106,6 +106,7 @@ package cva6_config_pkg;
       NrWbPorts: unsigned'(0),
       EnableAccelerator: bit'(0),
       RVS: bit'(1),
+      RVU: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),

core/include/cv64a6_imafdc_sv39_config_pkg.sv

@@ -107,6 +107,7 @@ package cva6_config_pkg;
       NrWbPorts: unsigned'(0),
       EnableAccelerator: bit'(0),
       RVS: bit'(1),
+      RVU: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),

core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv

@@ -114,6 +114,7 @@ package cva6_config_pkg;
       NrWbPorts: unsigned'(0),
       EnableAccelerator: bit'(0),
       RVS: bit'(1),
+      RVU: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),

core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv

@@ -107,6 +107,7 @@ package cva6_config_pkg;
       NrWbPorts: unsigned'(0),
       EnableAccelerator: bit'(0),
       RVS: bit'(1),
+      RVU: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),

core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv

@@ -107,6 +107,7 @@ package cva6_config_pkg;
       NrWbPorts: unsigned'(0),
       EnableAccelerator: bit'(0),
       RVS: bit'(1),
+      RVU: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),

core/include/cv64a6_imafdcv_sv39_config_pkg.sv

@@ -106,6 +106,7 @@ package cva6_config_pkg;
       NrWbPorts: unsigned'(0),
       EnableAccelerator: bit'(0),
       RVS: bit'(1),
+      RVU: bit'(1),
       HaltAddress: 64'h800,
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),

corev_apu/fpga/src/ariane_xilinx.sv

@@ -191,6 +191,7 @@ localparam config_pkg::cva6_cfg_t CVA6Cfg = '{
   NrWbPorts:             unsigned'(0),
   EnableAccelerator:     bit'(0),
   RVS:                   bit'(1),
+  RVU:                   bit'(1),
   HaltAddress:           dm::HaltAddress,
   ExceptionAddress:      dm::ExceptionAddress,
   DmBaseAddress:         ariane_soc::DebugBase,