Hardwire the reserved bits of the PMPCFG CSR to 0 #1368
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This realigns CVA6 with spike (openhwgroup#1346) Signed-off-by: Moritz Schneider <[email protected]>
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✔️ successful run, report available here. |
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@spidugu444 do you confirm this PR fix (partially) #1346 ? |
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With this PR PMPCFG CSR bit [6:5] has been hardwired to zero, which fix the discrepancy between spike and CVA6. |
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Currently, the PMPCFG CSRs are implemented as a full 8-bit register. However, the bits 5 and 6 are reserved according to the privilege spec. This patch hardwires these two bits to 0. This should also fix the discrepancy between spike and CVA6 for the PMPCFG CSRs (#1346 ). It might also lead to lower area/less luts used.