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Generate Zcb extension instructions (#1617)
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@AyoubJalali
AyoubJalali authored Nov 14, 2023
1 parent 97b6969 commit f9c7542
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Showing 5 changed files with 75 additions and 55 deletions.
9 changes: 8 additions & 1 deletion verif/env/corev-dv/custom/riscv_zcb_instr.sv
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Expand Up @@ -18,7 +18,14 @@
class riscv_zcb_instr_c extends riscv_custom_instr;

`uvm_object_utils(riscv_zcb_instr_c)
`uvm_object_new

function new(string name = "");
super.new(name);
rs1 = S0;
rs2 = S0;
rd = S0;
is_compressed = 1'b1;
endfunction : new

constraint rvc_rx_c {
// Registers specified by the three-bit rs1’, rs2’, and rd’
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7 changes: 6 additions & 1 deletion verif/regress/dv-generated-tests.sh
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Expand Up @@ -7,6 +7,11 @@
#
# Original Author: Ayoub JALALI ([email protected])

if [ -n "$RISCV_ZCB" ]; then
echo "Using RISCV_ZCB to support Zcb extension"
RISCV=$RISCV_ZCB
fi

if ! [ -n "$RISCV" ]; then
echo "Error: RISCV variable undefined"
return
Expand Down Expand Up @@ -108,7 +113,7 @@ printf "+=======================================================================
j=0
while [[ $j -lt ${#TEST_NAME[@]} ]];do
cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/
python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --isa_extension="zba,zbb,zbc,zbs" --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300
python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --isa_extension="zba,zbb,zbc,zbs,zcb" --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300
n=0
echo "Generate the test: ${TEST_NAME[j]}"
#this while loop detects the failed tests from the log file and remove them
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7 changes: 6 additions & 1 deletion verif/regress/dv-generated-xif-tests.sh
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Expand Up @@ -7,6 +7,11 @@
#
# Original Author: Ayoub JALALI ([email protected])

if [ -n "$RISCV_ZCB" ]; then
echo "Using RISCV_ZCB to support Zcb extension"
RISCV=$RISCV_ZCB
fi

if ! [ -n "$RISCV" ]; then
echo "Error: RISCV variable undefined"
return
Expand Down Expand Up @@ -74,7 +79,7 @@ printf "+=======================================================================
j=0
while [[ $j -lt ${#TEST_NAME[@]} ]];do
cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/
python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --isa_extension="zba,zbb,zbc,zbs" --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300
python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --isa_extension="zba,zbb,zbc,zbs,zcb" --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300
n=0
echo "Generate the test: ${TEST_NAME[j]}"
#this while loop detects the failed tests from the log file and remove them
Expand Down
12 changes: 8 additions & 4 deletions verif/regress/smoke-gen_tests.sh
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,11 @@
#
# Original Author: Ayoub JALALI - Thales

# where are the tools
if [ -n "$RISCV_ZCB" ]; then
echo "Using RISCV_ZCB to support Zcb extension"
RISCV=$RISCV_ZCB
fi

if ! [ -n "$RISCV" ]; then
echo "Error: RISCV variable undefined"
return
Expand All @@ -27,9 +31,9 @@ fi

cd verif/sim/
cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/
python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_arithmetic_basic_test_comp --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --isa_extension="zba,zbb,zbc,zbs" --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300
python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_load_store_test --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --isa_extension="zba,zbb,zbc,zbs" --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300
python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_unaligned_load_store_test --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --isa_extension="zba,zbb,zbc,zbs" --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300
python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_arithmetic_basic_test_comp --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --isa_extension="zba,zbb,zbc,zbs,zcb" --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300
python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_load_store_test --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --isa_extension="zba,zbb,zbc,zbs,zcb" --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300
python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_unaligned_load_store_test --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --isa_extension="zba,zbb,zbc,zbs,zcb" --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300
make clean_all

cd -
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