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core: re-parametrize the RVV interfaces
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@mp-17
mp-17 committed Dec 4, 2024
1 parent 4415e71 commit f695016
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Showing 4 changed files with 98 additions and 57 deletions.
65 changes: 14 additions & 51 deletions core/cva6.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -31,15 +31,7 @@ module cva6
rvfi_probes_instr_t instr;
},

// branchpredict scoreboard entry
// this is the struct which we will inject into the pipeline to guide the various
// units towards the correct branch decision and resolve
localparam type branchpredict_sbe_t = struct packed {
cf_t cf; // type of control flow prediction
logic [CVA6Cfg.VLEN-1:0] predict_address; // target address at which to jump, or not
},

localparam type exception_t = struct packed {
parameter type exception_t = struct packed {
logic [CVA6Cfg.XLEN-1:0] cause; // cause of exception
logic [CVA6Cfg.XLEN-1:0] tval; // additional information of causing exception (e.g.: instruction causing it),
// address of LD/ST fault
Expand All @@ -49,6 +41,14 @@ module cva6
logic valid;
},

// branchpredict scoreboard entry
// this is the struct which we will inject into the pipeline to guide the various
// units towards the correct branch decision and resolve
localparam type branchpredict_sbe_t = struct packed {
cf_t cf; // type of control flow prediction
logic [CVA6Cfg.VLEN-1:0] predict_address; // target address at which to jump, or not
},

// cache request ports
// I$ address translation requests
localparam type icache_areq_t = struct packed {
Expand Down Expand Up @@ -205,50 +205,13 @@ module cva6
logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] data_ruser;
},

// Accelerator - CVA6's
localparam type accelerator_req_t = struct packed {
logic req_valid;
logic resp_ready;
riscv::instruction_t insn;
logic [CVA6Cfg.XLEN-1:0] rs1;
logic [CVA6Cfg.XLEN-1:0] rs2;
fpnew_pkg::roundmode_e frm;
logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id;
logic store_pending;
logic acc_cons_en; // Invalidation interface
logic inval_ready; // Invalidation interface
},

localparam type accelerator_resp_t = struct packed {
logic req_ready;
logic resp_valid;
logic [CVA6Cfg.XLEN-1:0] result;
logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id;
exception_t exception;
logic store_pending;
logic store_complete;
logic load_complete;
logic [4:0] fflags;
logic fflags_valid;
logic inval_valid; // Invalidation interface
logic [63:0] inval_addr; // Invalidation interface
},
// Accelerator - CVA6
parameter type accelerator_req_t = logic,
parameter type accelerator_resp_t = logic,

// Accelerator - CVA6's MMU
localparam type acc_mmu_req_t = struct packed {
logic acc_mmu_misaligned_ex;
logic acc_mmu_req;
logic [CVA6Cfg.VLEN-1:0] acc_mmu_vaddr;
logic acc_mmu_is_store;
},

localparam type acc_mmu_resp_t = struct packed {
logic acc_mmu_dtlb_hit;
logic [CVA6Cfg.PPNW-1:0] acc_mmu_dtlb_ppn;
logic acc_mmu_valid;
logic [CVA6Cfg.PLEN-1:0] acc_mmu_paddr;
exception_t acc_mmu_exception;
},
parameter type acc_mmu_req_t = logic,
parameter type acc_mmu_resp_t = logic,

// AXI types
parameter type axi_ar_chan_t = struct packed {
Expand Down
10 changes: 5 additions & 5 deletions core/include/build_config_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -34,9 +34,9 @@ package build_config_pkg;
config_pkg::cva6_cfg_t cfg;

cfg.XLEN = CVA6Cfg.XLEN;
cfg.VLEN = (CVA6Cfg.XLEN == 32) ? 32 : 64;
cfg.PLEN = (CVA6Cfg.XLEN == 32) ? 34 : 56;
cfg.GPLEN = (CVA6Cfg.XLEN == 32) ? 34 : 41;
cfg.VLEN = CVA6Cfg.VLEN;
cfg.PLEN = CVA6Cfg.PLEN;
cfg.GPLEN = CVA6Cfg.GPLEN;
cfg.IS_XLEN32 = IS_XLEN32;
cfg.IS_XLEN64 = IS_XLEN64;
cfg.XLEN_ALIGN_BYTES = $clog2(CVA6Cfg.XLEN / 8);
Expand Down Expand Up @@ -79,7 +79,7 @@ package build_config_pkg;
cfg.RVZicntr = CVA6Cfg.RVZicntr;
cfg.RVZihpm = CVA6Cfg.RVZihpm;
cfg.NR_SB_ENTRIES = CVA6Cfg.NrScoreboardEntries;
cfg.TRANS_ID_BITS = $clog2(CVA6Cfg.NrScoreboardEntries);
cfg.TRANS_ID_BITS = CVA6Cfg.TRANS_ID_BITS;

cfg.FpPresent = bit'(FpPresent);
cfg.NSX = bit'(NSX);
Expand Down Expand Up @@ -162,7 +162,7 @@ package build_config_pkg;
cfg.ModeW = (CVA6Cfg.XLEN == 32) ? 1 : 4;
cfg.ASIDW = (CVA6Cfg.XLEN == 32) ? 9 : 16;
cfg.VMIDW = (CVA6Cfg.XLEN == 32) ? 7 : 14;
cfg.PPNW = (CVA6Cfg.XLEN == 32) ? 22 : 44;
cfg.PPNW = CVA6Cfg.PPNW;
cfg.GPPNW = (CVA6Cfg.XLEN == 32) ? 22 : 29;
cfg.MODE_SV = (CVA6Cfg.XLEN == 32) ? config_pkg::ModeSv32 : config_pkg::ModeSv39;
cfg.SV = (cfg.MODE_SV == config_pkg::ModeSv32) ? 32 : 39;
Expand Down
7 changes: 7 additions & 0 deletions core/include/config_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,11 @@ package config_pkg;
typedef struct packed {
// General Purpose Register Size (in bits)
int unsigned XLEN;
//
int unsigned VLEN;
int unsigned PLEN;
int unsigned GPLEN;
int unsigned PPNW;
// Atomic RISC-V extension
bit RVA;
// Bit manipulation RISC-V extension
Expand Down Expand Up @@ -204,6 +209,8 @@ package config_pkg;
bit unsigned UseSharedTlb;
// MMU depth of shared TLB
int unsigned SharedTlbDepth;
//
int unsigned TRANS_ID_BITS;
} cva6_user_cfg_t;

typedef struct packed {
Expand Down
73 changes: 72 additions & 1 deletion core/include/cv64a6_imafdcv_sv39_config_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -78,6 +78,10 @@ package cva6_config_pkg;

localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
XLEN: unsigned'(CVA6ConfigXlen),
VLEN: (unsigned'(CVA6ConfigXlen) == 32) ? 32 : 64,
PLEN: (unsigned'(CVA6ConfigXlen) == 32) ? 34 : 56,
GPLEN: (unsigned'(CVA6ConfigXlen) == 32) ? 34 : 41,
PPNW: (unsigned'(CVA6ConfigXlen) == 32) ? 22 : 44,
FpgaEn: bit'(CVA6ConfigFpgaEn),
TechnoCut: bit'(0),
SuperscalarEn: bit'(0),
Expand Down Expand Up @@ -155,6 +159,73 @@ package cva6_config_pkg;
SharedTlbDepth: int'(64),
NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs),
NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs),
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth)
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth),
TRANS_ID_BITS: $clog2(unsigned'(CVA6ConfigNrScoreboardEntries))
};

typedef struct packed {
logic [cva6_cfg.XLEN-1:0] cause; // cause of exception
logic [cva6_cfg.XLEN-1:0] tval; // additional information of causing exception (e.g.: instruction causing it),
// address of LD/ST fault
logic [cva6_cfg.GPLEN-1:0] tval2; // additional information when the causing exception in a guest exception
logic [31:0] tinst; // transformed instruction information
logic gva; // signals when a guest virtual address is written to tval
logic valid;
} exception_t;

// Accelerator - CVA6's
typedef struct packed {
logic req_valid;
logic resp_ready;
logic [31:0] insn;
logic [cva6_cfg.XLEN-1:0] rs1;
logic [cva6_cfg.XLEN-1:0] rs2;
fpnew_pkg::roundmode_e frm;
logic [cva6_cfg.TRANS_ID_BITS-1:0] trans_id;
logic store_pending;
logic acc_cons_en; // Invalidation interface
logic inval_ready; // Invalidation interface
} accelerator_req_t;

typedef struct packed {
logic req_ready;
logic resp_valid;
logic [cva6_cfg.XLEN-1:0] result;
logic [cva6_cfg.TRANS_ID_BITS-1:0] trans_id;
exception_t exception;
logic store_pending;
logic store_complete;
logic load_complete;
logic [4:0] fflags;
logic fflags_valid;
logic inval_valid; // Invalidation interface
logic [63:0] inval_addr; // Invalidation interface
} accelerator_resp_t;

// Accelerator - CVA6's MMU
typedef struct packed {
logic acc_mmu_misaligned_ex;
logic acc_mmu_req;
logic [cva6_cfg.VLEN-1:0] acc_mmu_vaddr;
logic acc_mmu_is_store;
} acc_mmu_req_t;

typedef struct packed {
logic acc_mmu_dtlb_hit;
logic [cva6_cfg.PPNW-1:0] acc_mmu_dtlb_ppn;
logic acc_mmu_valid;
logic [cva6_cfg.PLEN-1:0] acc_mmu_paddr;
exception_t acc_mmu_exception;
} acc_mmu_resp_t;

typedef struct packed {
accelerator_req_t acc_req; // Insn/mem
logic acc_mmu_en; // MMU
acc_mmu_resp_t acc_mmu_resp; // MMU
} cva6_to_acc_t;

typedef struct packed {
accelerator_resp_t acc_resp; // Insn/mem
acc_mmu_req_t acc_mmu_req; // MMU
} acc_to_cva6_t;
endpackage

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