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CORE-DV : Remove c.zext.w instruction from rv32zcb & update the zcb g…
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…eneration (#1585)
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@AyoubJalali
AyoubJalali authored Oct 31, 2023
1 parent 797f0a9 commit f301d69
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Showing 5 changed files with 557 additions and 46 deletions.
118 changes: 82 additions & 36 deletions verif/env/corev-dv/custom/riscv_zcb_instr.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -54,64 +54,110 @@ class riscv_zcb_instr_c extends riscv_custom_instr;
// Convert the instruction to assembly code
virtual function string convert2asm(string prefix = "");
string asm_str;
asm_str = format_string(get_instr_name(), MAX_INSTR_STR_LEN);
asm_str = format_string(get_cus_instr_name(), MAX_INSTR_STR_LEN);
case (instr_name)
C_LBU : asm_str = $sformatf("%0s %0s, %0s(%0s)", asm_str, rd.name(), get_imm(), rs1.name());
C_LH : asm_str = $sformatf("%0s %0s, %0s(%0s)", asm_str, rd.name(), get_imm(), rs1.name());
C_LHU : asm_str = $sformatf("%0s %0s, %0s(%0s)", asm_str, rd.name(), get_imm(), rs1.name());
C_SB : asm_str = $sformatf("%0s %0s, %0s(%0s)", asm_str, rs2.name(), get_imm(), rs1.name());
C_SH : asm_str = $sformatf("%0s %0s, %0s(%0s)", asm_str, rs2.name(), get_imm(), rs1.name());
C_MUL : asm_str = $sformatf("%0s %0s, %0s", asm_str, rd.name(), rs2.name());
C_ZEXT_B : asm_str = $sformatf("%0s %0s", asm_str, rd.name());
C_SEXT_B : asm_str = $sformatf("%0s %0s", asm_str, rd.name());
C_ZEXT_H : asm_str = $sformatf("%0s %0s", asm_str, rd.name());
C_SEXT_H : asm_str = $sformatf("%0s %0s", asm_str, rd.name());
C_ZEXT_W : asm_str = $sformatf("%0s %0s", asm_str, rd.name());
C_NOT : asm_str = $sformatf("%0s %0s", asm_str, rd.name());
C_LBU : asm_str = $sformatf("%0s%0s, %0s(%0s)", asm_str, rd.name(), get_imm(), rs1.name());
C_LH : asm_str = $sformatf("%0s%0s, %0s(%0s)", asm_str, rd.name(), get_imm(), rs1.name());
C_LHU : asm_str = $sformatf("%0s%0s, %0s(%0s)", asm_str, rd.name(), get_imm(), rs1.name());
C_SB : asm_str = $sformatf("%0s%0s, %0s(%0s)", asm_str, rs2.name(), get_imm(), rs1.name());
C_SH : asm_str = $sformatf("%0s%0s, %0s(%0s)", asm_str, rs2.name(), get_imm(), rs1.name());
C_MUL : asm_str = $sformatf("%0s%0s, %0s", asm_str, rd.name(), rs2.name());
C_ZEXT_B : asm_str = $sformatf("%0s%0s", asm_str, rd.name());
C_SEXT_B : asm_str = $sformatf("%0s%0s", asm_str, rd.name());
C_ZEXT_H : asm_str = $sformatf("%0s%0s", asm_str, rd.name());
C_SEXT_H : asm_str = $sformatf("%0s%0s", asm_str, rd.name());
C_ZEXT_W : asm_str = $sformatf("%0s%0s", asm_str, rd.name());
C_NOT : asm_str = $sformatf("%0s%0s", asm_str, rd.name());
endcase
return asm_str.tolower();
endfunction : convert2asm

// Convert the instruction to assembly code
virtual function string convert2bin(string prefix = "");
string binary;
case (instr_name) inside
//`uvm_info(`gfn, $sformatf("rs1 = %0s, imm = %b,
C_LBU:
binary = $sformatf("0x%4h", {get_func6(), rs1, imm[0], imm[1], rd, get_c_opcode()});
C_LHU:
binary = $sformatf("0x%4h", {get_func6(), rs1, 1'b0, imm[1], rd, get_c_opcode()});
C_LH:
binary = $sformatf("0x%4h", {get_func6(), rs1 , 1'b1, imm[1],rd , get_c_opcode()});
C_SB:
binary = $sformatf("0x%4h", {get_func6(), rs1, imm[0], imm[1] ,rs2 , get_c_opcode()});
C_SH:
binary = $sformatf("0x%4h", {get_func6(), rs1, 1'b0, imm[1], rs2, get_c_opcode()});
C_ZEXT_B:
binary = $sformatf("0x%4h", {get_func6(), rd, 5'b11000, get_c_opcode()});
C_SEXT_B:
binary = $sformatf("0x%4h", {get_func6(), rd, 5'b11001, get_c_opcode()});
C_ZEXT_H:
binary = $sformatf("0x%4h", {get_func6(), rd, 5'b11010, get_c_opcode()});
C_SEXT_H:
binary = $sformatf("0x%4h", {get_func6(), rd, 5'b11011, get_c_opcode()});
C_ZEXT_W:
binary = $sformatf("0x%4h", {get_func6(), rd, 5'b11100, get_c_opcode()});
C_NOT:
binary = $sformatf("0x%4h", {get_func6(), rd, 5'b11101, get_c_opcode()});
C_MUL:
binary = $sformatf("0x%4h", {get_func6(), rd, 2'b10, rs2, get_c_opcode()});
default : `uvm_fatal(`gfn, $sformatf("Unsupported instruction %0s", instr_name.name()))
endcase
return {prefix, binary};
endfunction : convert2bin

//TODO- work-around : Can't use the original methode of riscv_instr.sv
//so I create the same one with diffrent name
virtual function string get_cus_instr_name();
get_cus_instr_name = instr_name.name();
foreach(get_cus_instr_name[i]) begin
if (get_cus_instr_name[i] == "_") begin
get_cus_instr_name[i] = ".";
end
end
return get_cus_instr_name;
endfunction

virtual function bit [1:0] get_c_opcode();
case (instr_name) inside
C_LBU,C_LH,C_LHU,C_SB,C_SH : get_c_opcode = 2'b00;
C_MUL,C_ZEXT_B,C_SEXT_B,C_ZEXT_H,
C_SEXT_H,C_ZEXT_W : get_c_opcode = 2'b01;
C_MUL,C_ZEXT_B,C_SEXT_B,
C_SEXT_H,C_ZEXT_H,C_ZEXT_W : get_c_opcode = 2'b01;
endcase
endfunction

virtual function bit [2:0] get_func3();
virtual function bit [5:0] get_func6();
case (instr_name) inside
C_LBU : get_func3 = 3'b100;
C_LH : get_func3 = 3'b100;
C_LHU : get_func3 = 3'b100;
C_SB : get_func3 = 3'b100;
C_SH : get_func3 = 3'b100;
C_MUL : get_func3 = 3'b100;
C_ZEXT_B : get_func3 = 3'b100;
C_SEXT_B : get_func3 = 3'b100;
C_ZEXT_H : get_func3 = 3'b100;
C_SEXT_H : get_func3 = 3'b100;
C_ZEXT_W : get_func3 = 3'b100;
C_NOT : get_func3 = 3'b100;
C_LBU : get_func6 = 6'b100000;
C_LH : get_func6 = 6'b100001;
C_LHU : get_func6 = 6'b100001;
C_SB : get_func6 = 6'b100010;
C_SH : get_func6 = 6'b100011;
C_MUL : get_func6 = 6'b100111;
C_ZEXT_B : get_func6 = 6'b100111;
C_SEXT_B : get_func6 = 6'b100111;
C_ZEXT_H : get_func6 = 6'b100111;
C_SEXT_H : get_func6 = 6'b100111;
C_ZEXT_W : get_func6 = 6'b100111;
C_NOT : get_func6 = 6'b100111;
endcase
endfunction

virtual function void set_rand_mode();
case (instr_name) inside
"C_LBU", "C_LH","C_LHU" : begin
C_LBU, C_LH, C_LHU : begin
has_rs2 = 1'b0;
end
"C_SB", "C_SH" : begin
C_SB, C_SH : begin
has_rd = 1'b0;
end
"C_MUL" : begin
C_MUL : begin
has_rs1 = 1'b0;
has_imm = 1'b0;
end
"C_ZEXT_B", "C_SEXT_B",
"C_ZEXT_H", "C_SEXT_H",
"C_ZEXT_W", "C_NOT" : begin
C_ZEXT_B, C_SEXT_B,
C_ZEXT_H, C_SEXT_H,
C_NOT,C_ZEXT_W : begin
has_rs1 = 1'b0;
has_rs2 = 1'b0;
has_imm = 1'b0;
Expand All @@ -134,8 +180,8 @@ class riscv_zcb_instr_c extends riscv_custom_instr;
C_LBU,C_LH,C_LHU,C_SB,C_SH,
C_MUL,
C_ZEXT_B,C_SEXT_B,C_ZEXT_H,
C_SEXT_H,C_ZEXT_W,
C_NOT
C_SEXT_H,
C_NOT,C_ZEXT_W
});
endfunction

Expand Down
19 changes: 9 additions & 10 deletions verif/env/corev-dv/custom/rv32zcb_instr.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -9,15 +9,14 @@
// Original Author: Ayoub JALALI ([email protected])
// ------------------------------------------------------------------------------ //

`DEFINE_ZCB_INSTR(C_LBU, R_FORMAT, ARITHMETIC, RV32X, UIMM)
`DEFINE_ZCB_INSTR(C_LH, R_FORMAT, ARITHMETIC, RV32X, UIMM)
`DEFINE_ZCB_INSTR(C_LHU, R_FORMAT, ARITHMETIC, RV32X, UIMM)
`DEFINE_ZCB_INSTR(C_SB, R_FORMAT, ARITHMETIC, RV32X, UIMM)
`DEFINE_ZCB_INSTR(C_SH, R_FORMAT, ARITHMETIC, RV32X, UIMM)
`DEFINE_ZCB_INSTR(C_LBU, CL_FORMAT, LOAD, RV32X, UIMM)
`DEFINE_ZCB_INSTR(C_LH, CL_FORMAT, LOAD, RV32X, UIMM)
`DEFINE_ZCB_INSTR(C_LHU, CL_FORMAT, LOAD, RV32X, UIMM)
`DEFINE_ZCB_INSTR(C_SB, CS_FORMAT, STORE, RV32X, UIMM)
`DEFINE_ZCB_INSTR(C_SH, CS_FORMAT, STORE, RV32X, UIMM)
`DEFINE_ZCB_INSTR(C_MUL, R_FORMAT, ARITHMETIC, RV32X)
`DEFINE_ZCB_INSTR(C_ZEXT_B, R_FORMAT, LOGICAL, RV32X)
`DEFINE_ZCB_INSTR(C_SEXT_B, R_FORMAT, LOGICAL, RV32X)
`DEFINE_ZCB_INSTR(C_ZEXT_H, R_FORMAT, LOGICAL, RV32X)
`DEFINE_ZCB_INSTR(C_SEXT_H, R_FORMAT, LOGICAL, RV32X)
`DEFINE_ZCB_INSTR(C_ZEXT_W, R_FORMAT, LOGICAL, RV32X)
`DEFINE_ZCB_INSTR(C_ZEXT_B, R_FORMAT, ARITHMETIC, RV32X)
`DEFINE_ZCB_INSTR(C_SEXT_B, R_FORMAT, ARITHMETIC, RV32X)
`DEFINE_ZCB_INSTR(C_ZEXT_H, R_FORMAT, ARITHMETIC, RV32X)
`DEFINE_ZCB_INSTR(C_SEXT_H, R_FORMAT, ARITHMETIC, RV32X)
`DEFINE_ZCB_INSTR(C_NOT, R_FORMAT, LOGICAL, RV32X)
13 changes: 13 additions & 0 deletions verif/env/corev-dv/custom/rv64zcb_instr.sv
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Original file line number Diff line number Diff line change
@@ -0,0 +1,13 @@
// Copyright 2023 Thales DIS
// Copyright 2022 OpenHW Group
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
// You may obtain a copy of the License at https://solderpad.org/licenses/
//
// Original Author: Ayoub JALALI ([email protected])
// ------------------------------------------------------------------------------ //

`DEFINE_ZCB_INSTR(C_ZEXT_W, R_FORMAT, ARITHMETIC, RV64X)

2 changes: 2 additions & 0 deletions verif/env/corev-dv/cva6_instr_test_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -24,11 +24,13 @@ package cva6_instr_test_pkg;
`include "cva6_asm_program_gen.sv"
`include "cva6_instr_base_test.sv"
`include "cva6_instr_hazard_test.sv"
`include "cva6_load_store_instr_lib.sv"
`include "cvxif_custom_instr.sv"
`include "riscv_zicond_instr.sv"
`include "riscv_zcb_instr.sv"
`include "rv32x_instr.sv"
`include "rv32zicond_instr.sv"
`include "rv32zcb_instr.sv"
`include "rv64zcb_instr.sv"

endpackage : cva6_instr_test_pkg;
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