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superscalar: add a second issue port (#2209)
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@cathales
cathales authored Jun 9, 2024
1 parent 424eca6 commit eac60af
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Showing 11 changed files with 763 additions and 574 deletions.
2 changes: 0 additions & 2 deletions core/branch_unit.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -33,8 +33,6 @@ module branch_unit #(
input logic [CVA6Cfg.VLEN-1:0] pc_i,
// Instruction is compressed - ISSUE_STAGE
input logic is_compressed_instr_i,
// any functional unit is valid, check that there is no accidental mis-predict - TO_BE_COMPLETED
input logic fu_valid_i,
// Branch unit instruction is valid - ISSUE_STAGE
input logic branch_valid_i,
// ALU branch compare result - ALU
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6 changes: 3 additions & 3 deletions core/cache_subsystem/cache_ctrl.sv
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Expand Up @@ -311,9 +311,9 @@ module cache_ctrl
// two memory look-ups on a single-ported SRAM and therefore is non-atomic
if (!mshr_index_matches_i) begin
// store data, write dirty bit
req_o = hit_way_q;
addr_o = mem_req_q.index;
we_o = 1'b1;
req_o = hit_way_q;
addr_o = mem_req_q.index;
we_o = 1'b1;

be_o.vldrty = hit_way_q;

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36 changes: 21 additions & 15 deletions core/cva6.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -370,28 +370,28 @@ module cva6
// --------------
// ISSUE <-> EX
// --------------
logic [CVA6Cfg.VLEN-1:0] rs1_forwarding_id_ex; // unregistered version of fu_data_o.operanda
logic [CVA6Cfg.VLEN-1:0] rs2_forwarding_id_ex; // unregistered version of fu_data_o.operandb
logic [SUPERSCALAR:0][CVA6Cfg.VLEN-1:0] rs1_forwarding_id_ex; // unregistered version of fu_data_o.operanda
logic [SUPERSCALAR:0][CVA6Cfg.VLEN-1:0] rs2_forwarding_id_ex; // unregistered version of fu_data_o.operandb

fu_data_t fu_data_id_ex;
fu_data_t [SUPERSCALAR:0] fu_data_id_ex;
logic [CVA6Cfg.VLEN-1:0] pc_id_ex;
logic is_compressed_instr_id_ex;
logic [31:0] tinst_ex;
logic [SUPERSCALAR:0][31:0] tinst_ex;
// fixed latency units
logic flu_ready_ex_id;
logic [CVA6Cfg.TRANS_ID_BITS-1:0] flu_trans_id_ex_id;
logic flu_valid_ex_id;
logic [CVA6Cfg.XLEN-1:0] flu_result_ex_id;
exception_t flu_exception_ex_id;
// ALU
logic alu_valid_id_ex;
logic [SUPERSCALAR:0] alu_valid_id_ex;
// Branches and Jumps
logic branch_valid_id_ex;
logic [SUPERSCALAR:0] branch_valid_id_ex;

branchpredict_sbe_t branch_predict_id_ex;
logic resolve_branch_ex_id;
// LSU
logic lsu_valid_id_ex;
logic [SUPERSCALAR:0] lsu_valid_id_ex;
logic lsu_ready_ex_id;

logic [CVA6Cfg.TRANS_ID_BITS-1:0] load_trans_id_ex_id;
Expand All @@ -404,10 +404,10 @@ module cva6
logic store_valid_ex_id;
exception_t store_exception_ex_id;
// MULT
logic mult_valid_id_ex;
logic [SUPERSCALAR:0] mult_valid_id_ex;
// FPU
logic fpu_ready_ex_id;
logic fpu_valid_id_ex;
logic [SUPERSCALAR:0] fpu_valid_id_ex;
logic [1:0] fpu_fmt_id_ex;
logic [2:0] fpu_rm_id_ex;
logic [CVA6Cfg.TRANS_ID_BITS-1:0] fpu_trans_id_ex_id;
Expand All @@ -427,15 +427,15 @@ module cva6
logic acc_resp_fflags_valid;
logic single_step_acc_commit;
// CSR
logic csr_valid_id_ex;
logic [SUPERSCALAR:0] csr_valid_id_ex;
logic csr_hs_ld_st_inst_ex;
// CVXIF
logic [CVA6Cfg.TRANS_ID_BITS-1:0] x_trans_id_ex_id;
logic [CVA6Cfg.XLEN-1:0] x_result_ex_id;
logic x_valid_ex_id;
exception_t x_exception_ex_id;
logic x_we_ex_id;
logic x_issue_valid_id_ex;
logic [SUPERSCALAR:0] x_issue_valid_id_ex;
logic x_issue_ready_ex_id;
logic [31:0] x_off_instr_id_ex;
// --------------
Expand All @@ -462,7 +462,7 @@ module cva6
// --------------
// RVFI
// --------------
logic [CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_issue_pointer;
logic [ariane_pkg::SUPERSCALAR:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_issue_pointer;
logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_commit_pointer;
// --------------
// COMMIT <-> ID
Expand Down Expand Up @@ -1396,7 +1396,7 @@ module cva6
.issue_instr_i (issue_instr_id_acc),
.issue_instr_hs_i (issue_instr_hs_id_acc),
.issue_stall_o (stall_acc_id),
.fu_data_i (fu_data_id_ex),
.fu_data_i (fu_data_id_ex[0]),
.commit_instr_i (commit_instr_id_commit),
.commit_st_barrier_i (fence_i_commit_controller | fence_commit_controller),
.acc_trans_id_o (acc_trans_id_ex_id),
Expand Down Expand Up @@ -1626,8 +1626,8 @@ module cva6
.commit_pointer_i(rvfi_commit_pointer),

.flush_unissued_instr_i(flush_unissued_instr_ctrl_id),
.decoded_instr_valid_i (issue_entry_valid_id_issue[0]),
.decoded_instr_ack_i (issue_instr_issue_id[0]),
.decoded_instr_valid_i (issue_entry_valid_id_issue),
.decoded_instr_ack_i (issue_instr_issue_id),

.rs1_forwarding_i(rs1_forwarding_id_ex),
.rs2_forwarding_i(rs2_forwarding_id_ex),
Expand All @@ -1649,5 +1649,11 @@ module cva6

);

//pragma translate_off
initial begin
assert (!(ariane_pkg::SUPERSCALAR && CVA6Cfg.EnableAccelerator))
else $fatal(1, "Accelerator is not supported by superscalar pipeline");
end
//pragma translate_on

endmodule // ariane
46 changes: 26 additions & 20 deletions core/cva6_rvfi.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -51,29 +51,29 @@ module cva6_rvfi
localparam logic [63:0] SMODE_STATUS_READ_MASK = ariane_pkg::smode_status_read_mask(CVA6Cfg);

logic flush;
logic issue_instr_ack;
logic [ariane_pkg::SUPERSCALAR:0] issue_instr_ack;
logic [ariane_pkg::SUPERSCALAR:0] fetch_entry_valid;
logic [ariane_pkg::SUPERSCALAR:0][31:0] instruction;
logic [ariane_pkg::SUPERSCALAR:0] is_compressed;
logic [ariane_pkg::SUPERSCALAR:0][31:0] truncated;

logic [CVA6Cfg.TRANS_ID_BITS-1:0] issue_pointer;
logic [ariane_pkg::SUPERSCALAR:0][CVA6Cfg.TRANS_ID_BITS-1:0] issue_pointer;
logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] commit_pointer;

logic flush_unissued_instr;
logic decoded_instr_valid;
logic decoded_instr_ack;
logic [ariane_pkg::SUPERSCALAR:0] decoded_instr_valid;
logic [ariane_pkg::SUPERSCALAR:0] decoded_instr_ack;

logic [CVA6Cfg.XLEN-1:0] rs1_forwarding;
logic [CVA6Cfg.XLEN-1:0] rs2_forwarding;
logic [ariane_pkg::SUPERSCALAR:0][CVA6Cfg.XLEN-1:0] rs1_forwarding;
logic [ariane_pkg::SUPERSCALAR:0][CVA6Cfg.XLEN-1:0] rs2_forwarding;

logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.VLEN-1:0] commit_instr_pc;
fu_op [CVA6Cfg.NrCommitPorts-1:0] commit_instr_op;
logic [CVA6Cfg.NrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rs1;
logic [CVA6Cfg.NrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rs2;
logic [CVA6Cfg.NrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rd;
logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] commit_instr_result;
logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.VLEN-1:0] commit_instr_valid;
logic [CVA6Cfg.NrCommitPorts-1:0] commit_instr_valid;

logic [CVA6Cfg.XLEN-1:0] ex_commit_cause;
logic ex_commit_valid;
Expand Down Expand Up @@ -174,7 +174,11 @@ module cva6_rvfi
issue_n = issue_q;
took0 = 1'b0;

if (issue_instr_ack) issue_n[0].valid = 1'b0;
for (int unsigned i = 0; i <= ariane_pkg::SUPERSCALAR; i++) begin
if (issue_instr_ack[i]) begin
issue_n[i].valid = 1'b0;
end
end

if (!issue_n[ariane_pkg::SUPERSCALAR].valid) begin
issue_n[ariane_pkg::SUPERSCALAR].valid = fetch_entry_valid[0];
Expand Down Expand Up @@ -229,16 +233,18 @@ module cva6_rvfi
always_comb begin : issue_fifo
mem_n = mem_q;

if (decoded_instr_valid && decoded_instr_ack && !flush_unissued_instr) begin
mem_n[issue_pointer] = '{
rs1_rdata: rs1_forwarding,
rs2_rdata: rs2_forwarding,
lsu_addr: '0,
lsu_rmask: '0,
lsu_wmask: '0,
lsu_wdata: '0,
instr: issue_q[0].instr
};
for (int unsigned i = 0; i <= ariane_pkg::SUPERSCALAR; i++) begin
if (decoded_instr_valid[i] && decoded_instr_ack[i] && !flush_unissued_instr) begin
mem_n[issue_pointer[i]] = '{
rs1_rdata: rs1_forwarding[i],
rs2_rdata: rs2_forwarding[i],
lsu_addr: '0,
lsu_rmask: '0,
lsu_wmask: '0,
lsu_wdata: '0,
instr: issue_q[i].instr
};
end
end

if (lsu_rmask != 0) begin
Expand Down Expand Up @@ -266,7 +272,7 @@ module cva6_rvfi
always_ff @(posedge clk_i) begin
for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
logic exception;
exception = commit_instr_valid[i][0] && ex_commit_valid;
exception = commit_instr_valid[i] && ex_commit_valid;
rvfi_instr_o[i].valid <= (commit_ack[i] && !ex_commit_valid) ||
(exception && (ex_commit_cause == riscv::ENV_CALL_MMODE ||
ex_commit_cause == riscv::ENV_CALL_SMODE ||
Expand Down Expand Up @@ -350,7 +356,7 @@ module cva6_rvfi
`CONNECT_RVFI_FULL(1'b1, mstatus, csr.mstatus_extended)

bit [31:0] mstatush_q;
`CONNECT_RVFI_FULL(1'b1, mstatush, mstatush_q)
`CONNECT_RVFI_FULL(1'b1, mstatush, mstatush_q)

`CONNECT_RVFI_FULL(1'b1, misa, IsaCode)

Expand Down
12 changes: 6 additions & 6 deletions core/cva6_rvfi_probes.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -28,15 +28,15 @@ module cva6_rvfi_probes
input logic [SUPERSCALAR:0][31:0] instruction_i,
input logic [SUPERSCALAR:0] is_compressed_i,

input logic [CVA6Cfg.TRANS_ID_BITS-1:0] issue_pointer_i,
input logic [ SUPERSCALAR : 0][CVA6Cfg.TRANS_ID_BITS-1:0] issue_pointer_i,
input logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] commit_pointer_i,

input logic flush_unissued_instr_i,
input logic decoded_instr_valid_i,
input logic decoded_instr_ack_i,
input logic [SUPERSCALAR:0] decoded_instr_valid_i,
input logic [SUPERSCALAR:0] decoded_instr_ack_i,

input logic [CVA6Cfg.XLEN-1:0] rs1_forwarding_i,
input logic [CVA6Cfg.XLEN-1:0] rs2_forwarding_i,
input logic [SUPERSCALAR:0][CVA6Cfg.VLEN-1:0] rs1_forwarding_i,
input logic [SUPERSCALAR:0][CVA6Cfg.VLEN-1:0] rs2_forwarding_i,

input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
input exception_t ex_commit_i,
Expand All @@ -63,7 +63,7 @@ module cva6_rvfi_probes
instr = '0;

instr.flush = flush_i;
instr.issue_instr_ack = issue_instr_ack_i[0];
instr.issue_instr_ack = issue_instr_ack_i;
instr.fetch_entry_valid = fetch_entry_valid_i;
instr.instruction = instruction_i;
instr.is_compressed = is_compressed_i;
Expand Down
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