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@AngelaGonzalezMarino
AngelaGonzalezMarino committed Feb 19, 2024
1 parent 7515e6a commit e8425a3
Showing 1 changed file with 19 additions and 36 deletions.
55 changes: 19 additions & 36 deletions core/mmu_unify/cva6_mmu.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -393,9 +393,7 @@ module cva6_mmu
};
else
icache_areq_o.fetch_exception = {
riscv::INSTR_ACCESS_FAULT,
{{riscv::XLEN - riscv::VLEN{1'b0}}, icache_areq_i.fetch_vaddr},
1'b1
riscv::INSTR_ACCESS_FAULT,{{riscv::XLEN - riscv::VLEN{1'b0}}, icache_areq_i.fetch_vaddr},1'b1
};
icache_areq_o.fetch_valid = 1'b0;
// ---------
Expand All @@ -404,7 +402,7 @@ module cva6_mmu
// if we hit the ITLB output the request signal immediately
if (itlb_lu_hit) begin
icache_areq_o.fetch_valid = icache_areq_i.fetch_req;
if (HYP_EXT==1 && iaccess_err[HYP_EXT]) begin
if (HYP_EXT==1 && iaccess_err[HYP_EXT])
icache_areq_o.fetch_exception = {
riscv::INSTR_GUEST_PAGE_FAULT,
{{riscv::XLEN-riscv::VLEN{1'b0}}, icache_areq_i.fetch_vaddr},
Expand All @@ -414,9 +412,9 @@ module cva6_mmu
1'b1
};
// we got an access error
end else if (iaccess_err[0]) begin
else if (iaccess_err[0])
// throw a page fault
if(HYP_EXT==1) begin
if(HYP_EXT==1)
icache_areq_o.fetch_exception = {
riscv::INSTR_PAGE_FAULT,
{{riscv::XLEN-riscv::VLEN{1'b0}}, icache_areq_i.fetch_vaddr},
Expand All @@ -425,17 +423,12 @@ module cva6_mmu
enable_translation_i[HYP_EXT*2],
1'b1
};
end
else begin
else
icache_areq_o.fetch_exception = {
riscv::INSTR_PAGE_FAULT,
{{riscv::XLEN - riscv::VLEN{1'b0}}, icache_areq_i.fetch_vaddr},
1'b1
riscv::INSTR_PAGE_FAULT,{{riscv::XLEN - riscv::VLEN{1'b0}}, icache_areq_i.fetch_vaddr},1'b1
};
end

end else if (!pmp_instr_allow) begin
if(HYP_EXT==1) begin
else if (!pmp_instr_allow) begin
if(HYP_EXT==1)
icache_areq_o.fetch_exception = {
riscv::INSTR_ACCESS_FAULT,
{riscv::XLEN '(icache_areq_i.fetch_vaddr)},
Expand All @@ -444,12 +437,10 @@ module cva6_mmu
enable_translation_i[HYP_EXT*2],
1'b1
};
end
else begin
else
icache_areq_o.fetch_exception = {
riscv::INSTR_ACCESS_FAULT, riscv::XLEN '(icache_areq_i.fetch_vaddr), 1'b1
};
end
end
end else begin
// ---------
Expand All @@ -459,7 +450,7 @@ module cva6_mmu
if (ptw_active && walking_instr) begin
icache_areq_o.fetch_valid = ptw_error[0] | ptw_access_exception;
if (ptw_error[0]) begin
if (HYP_EXT==1 && ptw_error[HYP_EXT]) begin
if (HYP_EXT==1 && ptw_error[HYP_EXT])
icache_areq_o.fetch_exception = {
riscv::INSTR_GUEST_PAGE_FAULT,
{{riscv::XLEN-riscv::VLEN{1'b0}}, update_vaddr},
Expand All @@ -468,8 +459,8 @@ module cva6_mmu
enable_translation_i[2*HYP_EXT],
1'b1
};
end else begin
if (HYP_EXT==1) begin
else
if (HYP_EXT==1)
icache_areq_o.fetch_exception = {
riscv::INSTR_PAGE_FAULT,
{{riscv::XLEN-riscv::VLEN{1'b0}}, update_vaddr},
Expand All @@ -478,17 +469,14 @@ module cva6_mmu
enable_translation_i[2*HYP_EXT],
1'b1
};
end
else begin
else
icache_areq_o.fetch_exception = {
riscv::INSTR_PAGE_FAULT, {{riscv::XLEN - riscv::VLEN{1'b0}}, update_vaddr}, 1'b1
};
end
end
end
// TODO(moschn,zarubaf): What should the value of tval be in this case?
else begin
if(HYP_EXT==1) begin
else
if(HYP_EXT==1)
icache_areq_o.fetch_exception = {
riscv::INSTR_ACCESS_FAULT,
{{riscv::XLEN-riscv::VLEN{1'b0}}, update_vaddr},
Expand All @@ -497,35 +485,30 @@ module cva6_mmu
enable_translation_i[HYP_EXT*2],
1'b1
};
end
else begin
else
icache_areq_o.fetch_exception = {
riscv::INSTR_ACCESS_FAULT, ptw_bad_paddr[0][riscv::PLEN-1:(riscv::PLEN > riscv::VLEN) ? (riscv::PLEN - riscv::VLEN) : 0], 1'b1
};
end
end
end
end
end

// if it didn't match any execute region throw an `Instruction Access Fault`
// or: if we are not translating, check PMPs immediately on the paddr
if ((!match_any_execute_region && (!ptw_error[0]|| HYP_EXT==0) ) || (!(|enable_translation_i[HYP_EXT:0]) && !pmp_instr_allow)) begin
if(HYP_EXT==1) begin
if(HYP_EXT==1)
icache_areq_o.fetch_exception = {
riscv::INSTR_ACCESS_FAULT,
{riscv::XLEN '(icache_areq_o.fetch_paddr)},
{riscv::GPLEN{1'b0}},
{riscv::XLEN{1'b0}},
enable_translation_i[HYP_EXT*2],
1'b1
};
end
else begin
};
else
icache_areq_o.fetch_exception = {
riscv::INSTR_ACCESS_FAULT, riscv::VLEN'(icache_areq_o.fetch_paddr[riscv::PLEN-1:(riscv::PLEN > riscv::VLEN) ? (riscv::PLEN - riscv::VLEN) : 0]), 1'b1
};
end
end
end

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