Populate instruction chapter in CV32A65X Design Document

openhwgroup · Feb 9, 2024 · dc783f0 · dc783f0
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diff --git a/docs/01_cva6_user/RISCV_Instructions.rst b/docs/01_cva6_user/RISCV_Instructions.rst
@@ -20,8 +20,8 @@
 
 *This chapter is applicable to all configurations.*
 
-RISC-V Instructions
-===================
+CVA6 RISC-V Instructions
+========================
 
 Introduction
 ------------------

diff --git a/docs/04_cv32a65x_design/source/CSRs.rst b/docs/04_cv32a65x_design/source/CSRs.rst
@@ -12,7 +12,7 @@ CSR
 ===
 
 .. toctree::
-   :hidden:
+   :maxdepth: 1
 
    csr_list
    csr

diff --git a/docs/04_cv32a65x_design/source/functionality.rst b/docs/04_cv32a65x_design/source/functionality.rst
@@ -13,7 +13,7 @@ Functionality
 =============
 
 .. toctree::
-   :hidden:
+   :maxdepth: 1
 
    instructions
    traps

diff --git a/docs/04_cv32a65x_design/source/instructions.rst b/docs/04_cv32a65x_design/source/instructions.rst
@@ -7,5 +7,25 @@
 
    Original Author: Jean-Roch COULON - Thales
 
+Instructions
+============
 
-.. include:: ../../01_cva6_user/RISCV_Instructions.rst
+The next first subchapter lists the extensions implemented in CVA6.
+By configuration, we can enable/disable the extensions.
+CV32A65X supports the extensions described in the next subchapters.
+RVZicond, RV32A and RVZifencei extensions are not supported by CV32A65X.
+
+
+.. toctree::
+   :maxdepth: 1
+
+   ../../01_cva6_user/RISCV_Instructions
+   ../../01_cva6_user/RISCV_Instructions_RV32I
+   ../../01_cva6_user/RISCV_Instructions_RV32M
+   ../../01_cva6_user/RISCV_Instructions_RV32C
+   ../../01_cva6_user/RISCV_Instructions_RV32ZCb
+   ../../01_cva6_user/RISCV_Instructions_RVZba
+   ../../01_cva6_user/RISCV_Instructions_RVZbb
+   ../../01_cva6_user/RISCV_Instructions_RVZbc
+   ../../01_cva6_user/RISCV_Instructions_RVZbs
+   ../../01_cva6_user/RISCV_Instructions_RVZicsr