doc: update MVENDORID CSR value (fix #1735) (#1753)

openhwgroup · Jan 10, 2024 · dc634c6 · dc634c6
1 parent 88ab5a9
commit dc634c6
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Showing 3 changed files with 6 additions and 6 deletions.
diff --git a/docs/csr-from-ip-xact/cv32a60x/csr.rst b/docs/csr-from-ip-xact/cv32a60x/csr.rst
@@ -3661,13 +3661,13 @@ This register provids the JEDEC manufacturer ID of the provider of the core.
    * - 31:7
      - bank
      - Bank
-     - 0xC0 
+     - 0xC
      - read-only
      - Contain encoding for number of one\-byte continuation codes discarding the parity bit\.
    * - 6:0
      - offset
      - Offset
-     - 0x20 
+     - 0x2
      - read-only
      - Contain encording for the final byte discarding the parity bit\.
 

diff --git a/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.md b/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.md
@@ -1118,8 +1118,8 @@ Instructions-retired counter for RDINSTRET instruction. Shadow of minstreth.
 This register provids the JEDEC manufacturer ID of the provider of the core.
 | BIT |  NAME       | displayName        |Reset| RIGHT  | Description                                                          |
 | --- | ----------- | ------------       |-----| ------ | -------------------------------------------------------------------- |
-| 31:7 | bank | Bank | 0xC0 | read-only  | Contain encoding for number of one\-byte continuation codes discarding the parity bit\.|
-| 6:0 | offset | Offset | 0x20 | read-only  | Contain encording for the final byte discarding the parity bit\.|
+| 31:7 | bank | Bank | 0xC | read-only  | Contain encoding for number of one\-byte continuation codes discarding the parity bit\.|
+| 6:0 | offset | Offset | 0x2 | read-only  | Contain encording for the final byte discarding the parity bit\.|
 
 ## MARCHID : Machine Architecture ID Register 
 ### *AddressOffset*: 'hF12 

diff --git a/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.yaml b/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.yaml
@@ -3604,7 +3604,7 @@ component:
             bitOffset: '7'
             resets:
               reset:
-                value: '0xC0'
+                value: '0xC'
                 mask: '0x1ffffff'
             bitWidth: '25'
             volatile: 'true'
@@ -3615,7 +3615,7 @@ component:
             bitOffset: '0'
             resets:
               reset:
-                value: '0x20'
+                value: '0x2'
                 mask: '0x7f'
             bitWidth: '7'
             volatile: 'true'