treewide: verible pass

core/acc_dispatcher.sv

@@ -27,7 +27,7 @@ module acc_dispatcher
     parameter type acc_resp_t = logic,
     parameter type accelerator_req_t = logic,
     parameter type accelerator_resp_t = logic,
-    parameter type acc_mmu_req_t  = logic,
+    parameter type acc_mmu_req_t = logic,
     parameter type acc_mmu_resp_t = logic,
     parameter type acc_cfg_t = logic,
     parameter acc_cfg_t AccCfg = '0
@@ -207,21 +207,21 @@ module acc_dispatcher
    *************************/
 
   accelerator_req_t acc_req;
-  logic     acc_req_valid;
-  logic     acc_req_ready;
+  logic             acc_req_valid;
+  logic             acc_req_ready;
 
   accelerator_req_t acc_req_int;
   spill_register #(
       .T(accelerator_req_t)
   ) i_accelerator_req_register (
-      .clk_i     (clk_i),
-      .rst_ni    (rst_ni),
-      .data_i    (acc_req),
-      .valid_i   (acc_req_valid),
-      .ready_o   (acc_req_ready),
-      .data_o    (acc_req_int),
-      .valid_o   (acc_req_o.acc_req.req_valid),
-      .ready_i   (acc_resp_i.acc_resp.req_ready)
+      .clk_i  (clk_i),
+      .rst_ni (rst_ni),
+      .data_i (acc_req),
+      .valid_i(acc_req_valid),
+      .ready_o(acc_req_ready),
+      .data_o (acc_req_int),
+      .valid_o(acc_req_o.acc_req.req_valid),
+      .ready_i(acc_resp_i.acc_resp.req_ready)
   );
 
   assign acc_req_o.acc_req.insn          = acc_req_int.insn;
@@ -234,8 +234,8 @@ module acc_dispatcher
   assign acc_req_o.acc_req.inval_ready   = inval_ready_i;
 
   // MMU interface
-  assign acc_req_o.acc_mmu_resp = acc_mmu_resp_i;
-  assign acc_req_o.acc_mmu_en   = acc_mmu_en_i;
+  assign acc_req_o.acc_mmu_resp          = acc_mmu_resp_i;
+  assign acc_req_o.acc_mmu_en            = acc_mmu_en_i;
 
   always_comb begin : accelerator_req_dispatcher
     // Do not fetch from the instruction queue
@@ -279,13 +279,13 @@ module acc_dispatcher
   logic acc_ld_disp;
   logic acc_st_disp;
 
-  assign acc_trans_id_o     = acc_resp_i.acc_resp.trans_id;
-  assign acc_result_o       = acc_resp_i.acc_resp.result;
-  assign acc_valid_o        = acc_resp_i.acc_resp.resp_valid;
-  assign acc_exception_o    = acc_resp_i.acc_resp.exception;
+  assign acc_trans_id_o = acc_resp_i.acc_resp.trans_id;
+  assign acc_result_o = acc_resp_i.acc_resp.result;
+  assign acc_valid_o = acc_resp_i.acc_resp.resp_valid;
+  assign acc_exception_o = acc_resp_i.acc_resp.exception;
   // Unpack the accelerator response
   assign acc_fflags_valid_o = acc_resp_i.acc_resp.fflags_valid;
-  assign acc_fflags_o       = acc_resp_i.acc_resp.fflags;
+  assign acc_fflags_o = acc_resp_i.acc_resp.fflags;
 
   // MMU interface
   assign acc_mmu_req_o = acc_resp_i.acc_mmu_req;
@@ -294,8 +294,8 @@ module acc_dispatcher
   assign acc_req_o.acc_req.resp_ready = 1'b1;
 
   // Signal dispatched load/store to issue stage
-  assign acc_ld_disp          = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_LOAD);
-  assign acc_st_disp          = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_STORE);
+  assign acc_ld_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_LOAD);
+  assign acc_st_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_STORE);
 
   // Cache invalidation
   assign inval_valid_o = acc_resp_i.acc_resp.inval_valid;
@@ -338,7 +338,7 @@ module acc_dispatcher
 
   // Set on store barrier. Clear when no store is pending.
   assign wait_acc_store_d = (wait_acc_store_q | commit_st_barrier_i) & acc_resp_i.acc_resp.store_pending;
-  assign ctrl_halt_o      = wait_acc_store_q;
+  assign ctrl_halt_o = wait_acc_store_q;
 
   /**************************
    *  Load/Store tracking   *

core/cache_subsystem/cva6_icache.sv

@@ -424,8 +424,8 @@ module cva6_icache
   logic [CVA6Cfg.ICACHE_SET_ASSOC_WIDTH-1:0] hit_idx;
 
   for (genvar i = 0; i < CVA6Cfg.ICACHE_SET_ASSOC; i++) begin : gen_tag_cmpsel
-    assign cl_hit[i]  = (cl_tag_rdata[i] == cl_tag_d) & vld_rdata[i];
-    assign cl_sel[i]  = cl_rdata[i][{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_WIDTH];
+    assign cl_hit[i] = (cl_tag_rdata[i] == cl_tag_d) & vld_rdata[i];
+    assign cl_sel[i] = cl_rdata[i][{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_WIDTH];
     assign cl_user[i] = CVA6Cfg.FETCH_USER_EN ? cl_ruser[i][{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_USER_WIDTH] : '0;
   end
 

core/cache_subsystem/wt_dcache_missunit.sv

@@ -91,8 +91,8 @@ module wt_dcache_missunit
   // 010: word
   // 011: dword
   // 111: DCACHE line
-  function automatic logic [CVA6Cfg.PLEN-1:0] paddrSizeAlign(input logic [CVA6Cfg.PLEN-1:0] paddr,
-                                                             input logic [2:0] size);
+  function automatic logic [CVA6Cfg.PLEN-1:0] paddrSizeAlign(
+      input logic [CVA6Cfg.PLEN-1:0] paddr, input logic [2:0] size);
     logic [CVA6Cfg.PLEN-1:0] out;
     out = paddr;
     unique case (size)

core/cache_subsystem/wt_dcache_wbuffer.sv

@@ -136,8 +136,8 @@ module wt_dcache_wbuffer
 
   // openpiton requires the data to be replicated in case of smaller sizes than dwords
   function automatic logic [CVA6Cfg.XLEN-1:0] repData64(
-      input logic [CVA6Cfg.XLEN-1:0] data, input logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] offset,
-      input logic [1:0] size);
+      input logic [CVA6Cfg.XLEN-1:0] data,
+      input logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] offset, input logic [1:0] size);
     logic [CVA6Cfg.XLEN-1:0] out;
     unique case (size)
       2'b00:   for (int k = 0; k < 8; k++) out[k*8+:8] = data[offset*8+:8];  // byte
@@ -149,8 +149,8 @@ module wt_dcache_wbuffer
   endfunction : repData64
 
   function automatic logic [CVA6Cfg.XLEN-1:0] repData32(
-      input logic [CVA6Cfg.XLEN-1:0] data, input logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] offset,
-      input logic [1:0] size);
+      input logic [CVA6Cfg.XLEN-1:0] data,
+      input logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] offset, input logic [1:0] size);
     logic [CVA6Cfg.XLEN-1:0] out;
     unique case (size)
       2'b00:   for (int k = 0; k < 4; k++) out[k*8+:8] = data[offset*8+:8];  // byte

core/cva6.sv

@@ -212,11 +212,11 @@ module cva6
     },
 
     // Accelerator - CVA6
-    parameter type accelerator_req_t = logic,
+    parameter type accelerator_req_t  = logic,
     parameter type accelerator_resp_t = logic,
 
     // Accelerator - CVA6's MMU
-    parameter type acc_mmu_req_t = logic,
+    parameter type acc_mmu_req_t  = logic,
     parameter type acc_mmu_resp_t = logic,
 
     // AXI types

core/cva6_mmu/cva6_shared_tlb.sv

@@ -94,7 +94,8 @@ module cva6_shared_tlb #(
   shared_tag_t shared_tag_wr;
   shared_tag_t [SHARED_TLB_WAYS-1:0] shared_tag_rd;
 
-  logic [CVA6Cfg.SharedTlbDepth-1:0][SHARED_TLB_WAYS-1:0] shared_tag_valid_q, shared_tag_valid_d;
+  logic [CVA6Cfg.SharedTlbDepth-1:0][SHARED_TLB_WAYS-1:0]
+      shared_tag_valid_q, shared_tag_valid_d;
 
   logic [               SHARED_TLB_WAYS-1:0] shared_tag_valid;
 
@@ -122,7 +123,8 @@ module cva6_shared_tlb #(
   logic [               SHARED_TLB_WAYS-1:0] pte_we;
   logic [$clog2(CVA6Cfg.SharedTlbDepth)-1:0] pte_addr;
 
-  logic [CVA6Cfg.PtLevels+HYP_EXT-1:0][(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1:0] vpn_d, vpn_q;
+  logic [CVA6Cfg.PtLevels+HYP_EXT-1:0][(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1:0]
+      vpn_d, vpn_q;
   logic [SHARED_TLB_WAYS-1:0][CVA6Cfg.PtLevels-1:0] vpn_match;
   logic [SHARED_TLB_WAYS-1:0][CVA6Cfg.PtLevels-1:0] page_match;
   logic [SHARED_TLB_WAYS-1:0][CVA6Cfg.PtLevels-1:0] level_match;

core/ex_stage.sv

@@ -30,7 +30,7 @@ module ex_stage
     parameter type icache_drsp_t = logic,
     parameter type lsu_ctrl_t = logic,
     parameter type x_result_t = logic,
-    parameter type acc_mmu_req_t  = logic,
+    parameter type acc_mmu_req_t = logic,
     parameter type acc_mmu_resp_t = logic
 ) (
     // Subsystem Clock - SUBSYSTEM
@@ -162,7 +162,7 @@ module ex_stage
     // accelerate port result is valid - ACC_DISPATCHER
     input logic acc_valid_i,
     // Accelerator MMU access
-    input acc_mmu_req_t  acc_mmu_req_i,
+    input acc_mmu_req_t acc_mmu_req_i,
     output acc_mmu_resp_t acc_mmu_resp_o,
     // Enable virtual memory translation - CSR_REGFILE
     input logic enable_translation_i,

core/frontend/frontend.sv

@@ -127,7 +127,8 @@ module frontend
   logic [CVA6Cfg.INSTR_PER_FETCH-1:0] rvi_return, rvi_call, rvi_branch, rvi_jalr, rvi_jump;
   logic [CVA6Cfg.INSTR_PER_FETCH-1:0][CVA6Cfg.VLEN-1:0] rvi_imm;
   // RVC branching
-  logic [CVA6Cfg.INSTR_PER_FETCH-1:0] rvc_branch, rvc_jump, rvc_jr, rvc_return, rvc_jalr, rvc_call;
+  logic [CVA6Cfg.INSTR_PER_FETCH-1:0]
+      rvc_branch, rvc_jump, rvc_jr, rvc_return, rvc_jalr, rvc_call;
   logic            [CVA6Cfg.INSTR_PER_FETCH-1:0][CVA6Cfg.VLEN-1:0] rvc_imm;
   // re-aligned instruction and address (coming from cache - combinationally)
   logic            [CVA6Cfg.INSTR_PER_FETCH-1:0][            31:0] instr;

core/include/build_config_pkg.sv

@@ -123,15 +123,17 @@ package build_config_pkg;
     cfg.AxiBurstWriteEn = CVA6Cfg.AxiBurstWriteEn;
 
     cfg.ICACHE_SET_ASSOC = CVA6Cfg.IcacheSetAssoc;
-    cfg.ICACHE_SET_ASSOC_WIDTH = CVA6Cfg.IcacheSetAssoc > 1 ? $clog2(CVA6Cfg.IcacheSetAssoc) : CVA6Cfg.IcacheSetAssoc;
+    cfg.ICACHE_SET_ASSOC_WIDTH = CVA6Cfg.IcacheSetAssoc > 1 ? $clog2(CVA6Cfg.IcacheSetAssoc) :
+        CVA6Cfg.IcacheSetAssoc;
     cfg.ICACHE_INDEX_WIDTH = ICACHE_INDEX_WIDTH;
     cfg.ICACHE_TAG_WIDTH = cfg.PLEN - ICACHE_INDEX_WIDTH;
     cfg.ICACHE_LINE_WIDTH = CVA6Cfg.IcacheLineWidth;
     cfg.ICACHE_USER_LINE_WIDTH = (CVA6Cfg.AxiUserWidth == 1) ? 4 : CVA6Cfg.IcacheLineWidth;
     cfg.DCacheType = CVA6Cfg.DCacheType;
     cfg.DcacheIdWidth = CVA6Cfg.DcacheIdWidth;
     cfg.DCACHE_SET_ASSOC = CVA6Cfg.DcacheSetAssoc;
-    cfg.DCACHE_SET_ASSOC_WIDTH = CVA6Cfg.DcacheSetAssoc > 1 ? $clog2(CVA6Cfg.DcacheSetAssoc) : CVA6Cfg.DcacheSetAssoc;
+    cfg.DCACHE_SET_ASSOC_WIDTH = CVA6Cfg.DcacheSetAssoc > 1 ? $clog2(CVA6Cfg.DcacheSetAssoc) :
+        CVA6Cfg.DcacheSetAssoc;
     cfg.DCACHE_INDEX_WIDTH = DCACHE_INDEX_WIDTH;
     cfg.DCACHE_TAG_WIDTH = cfg.PLEN - DCACHE_INDEX_WIDTH;
     cfg.DCACHE_LINE_WIDTH = CVA6Cfg.DcacheLineWidth;

core/include/cv64a6_imafdcv_sv39_config_pkg.sv

@@ -34,7 +34,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigAxiAddrWidth = 64;
   localparam CVA6ConfigAxiDataWidth = 64;
   localparam CVA6ConfigFetchUserEn = 0;
-  localparam CVA6ConfigFetchUserWidth = 1; // Just not to raise warnings
+  localparam CVA6ConfigFetchUserWidth = 1;  // Just not to raise warnings
   localparam CVA6ConfigDataUserEn = 0;
   localparam CVA6ConfigDataUserWidth = CVA6ConfigXlen;
 
@@ -177,23 +177,23 @@ package cva6_config_pkg;
     fpnew_pkg::roundmode_e             frm;
     logic [cva6_cfg.TRANS_ID_BITS-1:0] trans_id;
     logic                              store_pending;
-    logic                              acc_cons_en; // Invalidation interface
-    logic                              inval_ready; // Invalidation interface
+    logic                              acc_cons_en;    // Invalidation interface
+    logic                              inval_ready;    // Invalidation interface
   } accelerator_req_t;
 
   typedef struct packed {
-    logic                                 req_ready;
-    logic                                 resp_valid;
-    logic [cva6_cfg.XLEN-1:0]             result;
-    logic [cva6_cfg.TRANS_ID_BITS-1:0]    trans_id;
-    exception_t                           exception;
-    logic                                 store_pending;
-    logic                                 store_complete;
-    logic                                 load_complete;
-    logic [4:0]                           fflags;
-    logic                                 fflags_valid;
-    logic                                 inval_valid; // Invalidation interface
-    logic [63:0]                          inval_addr; // Invalidation interface
+    logic                              req_ready;
+    logic                              resp_valid;
+    logic [cva6_cfg.XLEN-1:0]          result;
+    logic [cva6_cfg.TRANS_ID_BITS-1:0] trans_id;
+    exception_t                        exception;
+    logic                              store_pending;
+    logic                              store_complete;
+    logic                              load_complete;
+    logic [4:0]                        fflags;
+    logic                              fflags_valid;
+    logic                              inval_valid;     // Invalidation interface
+    logic [63:0]                       inval_addr;      // Invalidation interface
   } accelerator_resp_t;
 
   // Accelerator - CVA6's MMU
@@ -213,13 +213,13 @@ package cva6_config_pkg;
   } acc_mmu_resp_t;
 
   typedef struct packed {
-    accelerator_req_t                     acc_req; // Insn/mem
-    logic                                 acc_mmu_en; // MMU
-    acc_mmu_resp_t                        acc_mmu_resp; // MMU
+    accelerator_req_t acc_req;       // Insn/mem
+    logic             acc_mmu_en;    // MMU
+    acc_mmu_resp_t    acc_mmu_resp;  // MMU
   } cva6_to_acc_t;
 
   typedef struct packed {
-    accelerator_resp_t                    acc_resp; // Insn/mem
-    acc_mmu_req_t                         acc_mmu_req; // MMU
+    accelerator_resp_t acc_resp;     // Insn/mem
+    acc_mmu_req_t      acc_mmu_req;  // MMU
   } acc_to_cva6_t;
 endpackage