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Revert "update pte_cva6_t and tlb_update_cva6_t data types to support…
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… hypervisor extension. Update all submodules to new data types as first step"

This reverts commit 257f6e0.
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@AngelaGonzalezMarino
AngelaGonzalezMarino committed Dec 15, 2023
1 parent fb94420 commit d7a3512
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Showing 5 changed files with 72 additions and 98 deletions.
24 changes: 5 additions & 19 deletions core/load_store_unit.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -171,26 +171,15 @@ module load_store_unit
// );
if (MMU_PRESENT) begin : gen_mmu

localparam HYP_EXT = 0; //CVA6Cfg.CVA6ConfigHExtEn
localparam ASID_LEN = (riscv::XLEN == 64) ? 16 : 9;
localparam VPN_LEN = (riscv::XLEN == 64) ? (HYP_EXT ? 29 : 27) : 20;
localparam VPN_LEN = (riscv::XLEN == 64) ? 27 : 20;
localparam PT_LEVELS = (riscv::XLEN == 64) ? 3 : 2;
localparam int unsigned mmu_ASID_WIDTH [HYP_EXT:0] = {ASID_WIDTH};

logic [mmu_ASID_WIDTH[0]-1:0] mmu_asid_i [HYP_EXT:0];
logic [mmu_ASID_WIDTH[0]-1:0] mmu_asid_to_be_flushed_i [HYP_EXT:0];
logic [riscv::VLEN-1:0] mmu_vaddr_to_be_flushed_i [HYP_EXT:0];
logic [riscv::VLEN-1:0] mmu_lsu_vaddr_i[HYP_EXT:0];

assign mmu_asid_i[0] = asid_i;
assign mmu_asid_to_be_flushed_i[0] =asid_to_be_flushed_i;
assign mmu_vaddr_to_be_flushed_i[0] =vaddr_to_be_flushed_i;
assign mmu_lsu_vaddr_i[0]= mmu_vaddr;
cva6_mmu #(
.CVA6Cfg (CVA6Cfg),
.INSTR_TLB_ENTRIES(ariane_pkg::INSTR_TLB_ENTRIES),
.DATA_TLB_ENTRIES (ariane_pkg::DATA_TLB_ENTRIES),
.ASID_WIDTH (mmu_ASID_WIDTH),
.ASID_WIDTH (ASID_WIDTH),
.ASID_LEN (ASID_LEN),
.VPN_LEN (VPN_LEN),
.PT_LEVELS (PT_LEVELS)
Expand All @@ -199,7 +188,7 @@ module load_store_unit
.misaligned_ex_i(misaligned_exception),
.lsu_is_store_i (st_translation_req),
.lsu_req_i (translation_req),
.lsu_vaddr_i (mmu_lsu_vaddr_i),
.lsu_vaddr_i (mmu_vaddr),
.lsu_valid_o (translation_valid),
.lsu_paddr_o (mmu_paddr),
.lsu_exception_o(mmu_exception),
Expand All @@ -210,14 +199,11 @@ module load_store_unit
.req_port_o (dcache_req_ports_o[0]),
// icache address translation requests
.icache_areq_i (icache_areq_i),
// .asid_to_be_flushed_i,
// .vaddr_to_be_flushed_i,
.asid_to_be_flushed_i,
.vaddr_to_be_flushed_i,
.icache_areq_o (icache_areq_o),
.pmpcfg_i,
.pmpaddr_i,
.asid_i(mmu_asid_i),
.asid_to_be_flushed_i(mmu_asid_to_be_flushed_i),
.vaddr_to_be_flushed_i(mmu_vaddr_to_be_flushed_i),
.*
);
end else begin : gen_no_mmu
Expand Down
64 changes: 29 additions & 35 deletions core/mmu_unify/cva6_mmu.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,11 +23,10 @@ import ariane_pkg::*;
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter int unsigned INSTR_TLB_ENTRIES = 4,
parameter int unsigned DATA_TLB_ENTRIES = 4,
parameter int unsigned ASID_WIDTH [HYP_EXT:0]= {1},
parameter int unsigned ASID_WIDTH = 1,
parameter int unsigned ASID_LEN = 1,
parameter int unsigned VPN_LEN = 1,
parameter int unsigned PT_LEVELS = 1,
parameter logic HYP_EXT = 0
parameter int unsigned PT_LEVELS = 1
) (
input logic clk_i,
input logic rst_ni,
Expand All @@ -42,7 +41,7 @@ import ariane_pkg::*;
// in the LSU as we distinguish load and stores, what we do here is simple address translation
input exception_t misaligned_ex_i,
input logic lsu_req_i, // request address translation
input logic [riscv::VLEN-1:0] lsu_vaddr_i[HYP_EXT:0], // virtual address in
input logic [riscv::VLEN-1:0] lsu_vaddr_i, // virtual address in
input logic lsu_is_store_i, // the translation is requested by a store
// if we need to walk the page table we can't grant in the same cycle
// Cycle 0
Expand All @@ -59,9 +58,9 @@ import ariane_pkg::*;
input logic mxr_i,
// input logic flag_mprv_i,
input logic [riscv::PPNW-1:0] satp_ppn_i,
input logic [ASID_WIDTH[0]-1:0] asid_i [HYP_EXT:0],
input logic [ASID_WIDTH[0]-1:0] asid_to_be_flushed_i [HYP_EXT:0],
input logic [riscv::VLEN-1:0] vaddr_to_be_flushed_i [HYP_EXT:0],
input logic [ASID_WIDTH-1:0] asid_i,
input logic [ASID_WIDTH-1:0] asid_to_be_flushed_i,
input logic [riscv::VLEN-1:0] vaddr_to_be_flushed_i,
input logic flush_tlb_i,
// Performance counters
output logic itlb_miss_o,
Expand Down Expand Up @@ -92,13 +91,12 @@ localparam type pte_cva6_t = struct packed {
localparam type tlb_update_cva6_t = struct packed {
// typedef struct packed {
logic valid; // valid flag
logic [HYP_EXT:0][PT_LEVELS-2:0] is_page; //
logic [PT_LEVELS-2:0] is_page; //
logic [VPN_LEN-1:0] vpn; //
logic [HYP_EXT:0][ASID_LEN-1:0] asid; //
pte_cva6_t [HYP_EXT:0] content;
logic [ASID_LEN-1:0] asid; //
pte_cva6_t content;
} ;


logic iaccess_err; // insufficient privilege to access this instruction page
logic daccess_err; // insufficient privilege to access this data page
logic ptw_active; // PTW is currently walking a page table
Expand All @@ -112,12 +110,12 @@ logic [riscv::VLEN-1:0] update_vaddr;
tlb_update_cva6_t update_itlb, update_dtlb, update_shared_tlb;

logic itlb_lu_access;
pte_cva6_t [HYP_EXT:0] itlb_content ;
pte_cva6_t itlb_content;
logic [PT_LEVELS-2:0] itlb_is_page;
logic itlb_lu_hit;

logic dtlb_lu_access;
pte_cva6_t [HYP_EXT:0] dtlb_content;
pte_cva6_t dtlb_content;
logic [PT_LEVELS-2:0] dtlb_is_page;
logic dtlb_lu_hit;

Expand All @@ -131,8 +129,6 @@ logic itlb_req;
assign itlb_lu_access = icache_areq_i.fetch_req;
assign dtlb_lu_access = lsu_req_i;

logic [riscv::VLEN-1:0] lu_vaddr_i [HYP_EXT:0];
assign lu_vaddr_i[0]=icache_areq_i.fetch_vaddr;

cva6_tlb #(
.CVA6Cfg (CVA6Cfg),
Expand All @@ -154,12 +150,11 @@ cva6_tlb #(
.lu_asid_i (asid_i),
.asid_to_be_flushed_i (asid_to_be_flushed_i),
.vaddr_to_be_flushed_i(vaddr_to_be_flushed_i),
.lu_vaddr_i (lu_vaddr_i),
.lu_vaddr_i (icache_areq_i.fetch_vaddr),
.lu_content_o (itlb_content),

.lu_is_page_o(itlb_is_page),
.lu_hit_o (itlb_lu_hit),
.v_st_enbl_i(1)
.lu_hit_o (itlb_lu_hit)
);

cva6_tlb #(
Expand All @@ -186,15 +181,14 @@ cva6_tlb #(
.lu_content_o (dtlb_content),

.lu_is_page_o(dtlb_is_page),
.lu_hit_o (dtlb_lu_hit),
.v_st_enbl_i(1)
.lu_hit_o (dtlb_lu_hit)
);

cva6_shared_tlb #(
.CVA6Cfg (CVA6Cfg),
.SHARED_TLB_DEPTH(64),
.SHARED_TLB_WAYS (2),
.ASID_WIDTH (ASID_WIDTH[0]),
.ASID_WIDTH (ASID_WIDTH),
.ASID_LEN (ASID_LEN),
.VPN_LEN(VPN_LEN),
.PT_LEVELS(PT_LEVELS),
Expand All @@ -208,7 +202,7 @@ cva6_shared_tlb #(
.enable_translation_i (enable_translation_i),
.en_ld_st_translation_i(en_ld_st_translation_i),

.asid_i (asid_i[0]),
.asid_i (asid_i),
// from TLBs
// did we miss?
.itlb_access_i(itlb_lu_access),
Expand All @@ -217,7 +211,7 @@ cva6_shared_tlb #(

.dtlb_access_i(dtlb_lu_access),
.dtlb_hit_i (dtlb_lu_hit),
.dtlb_vaddr_i (lsu_vaddr_i[0]),
.dtlb_vaddr_i (lsu_vaddr_i),

// to TLBs, update logic
.itlb_update_o(update_itlb),
Expand All @@ -238,7 +232,7 @@ cva6_shared_tlb #(

cva6_ptw #(
.CVA6Cfg (CVA6Cfg),
.ASID_WIDTH(ASID_WIDTH[0]),
.ASID_WIDTH(ASID_WIDTH),
.VPN_LEN(VPN_LEN),
.PT_LEVELS(PT_LEVELS),
.pte_cva6_t(pte_cva6_t),
Expand All @@ -263,7 +257,7 @@ cva6_ptw #(

.update_vaddr_o(update_vaddr),

.asid_i(asid_i[0]),
.asid_i(asid_i),

// from shared TLB
// did we miss?
Expand Down Expand Up @@ -318,16 +312,16 @@ localparam PPNWMin = (riscv::PPNW - 1 > 29) ? 29 : riscv::PPNW - 1;
assign icache_areq_o.fetch_paddr [11:0] = icache_areq_i.fetch_vaddr[11:0];
assign icache_areq_o.fetch_paddr [riscv::PLEN-1:PPNWMin+1] = //
(enable_translation_i) ? //
itlb_content[0].ppn[riscv::PPNW-1:(riscv::PPNW - (riscv::PLEN - PPNWMin-1))] : //
(riscv::PLEN-PPNWMin-1)'(icache_areq_i.fetch_vaddr[((riscv::PLEN > riscv::VLEN) ? riscv::VLEN : riscv::PLEN )-1:PPNWMin+1]);
itlb_content.ppn[riscv::PPNW-1:(riscv::PPNW - (riscv::PLEN - PPNWMin-1))] : //
riscv::PLEN'(icache_areq_i.fetch_vaddr[((riscv::PLEN > riscv::VLEN) ? riscv::VLEN : riscv::PLEN )-1:PPNWMin+1]);

genvar a;
generate

for (a=0; a < PT_LEVELS-1; a++) begin
assign icache_areq_o.fetch_paddr [PPNWMin-((VPN_LEN/PT_LEVELS)*(a)):PPNWMin-((VPN_LEN/PT_LEVELS)*(a+1))+1] = //
(enable_translation_i && (|itlb_is_page[a:0]==0)) ? //
itlb_content[0].ppn [(riscv::PPNW - (riscv::PLEN - PPNWMin-1)-((VPN_LEN/PT_LEVELS)*(a))-1):(riscv::PPNW - (riscv::PLEN - PPNWMin-1)-((VPN_LEN/PT_LEVELS)*(a+1)))] : //
itlb_content.ppn [(riscv::PPNW - (riscv::PLEN - PPNWMin-1)-((VPN_LEN/PT_LEVELS)*(a))-1):(riscv::PPNW - (riscv::PLEN - PPNWMin-1)-((VPN_LEN/PT_LEVELS)*(a+1)))] : //
icache_areq_i.fetch_vaddr[PPNWMin-((VPN_LEN/PT_LEVELS)*(a)):PPNWMin-((VPN_LEN/PT_LEVELS)*(a+1))+1];
end

Expand All @@ -342,8 +336,8 @@ always_comb begin : instr_interface
// 2. We got an access error because of insufficient permissions -> throw an access exception
icache_areq_o.fetch_exception = '0;
// Check whether we are allowed to access this memory region from a fetch perspective
iaccess_err = icache_areq_i.fetch_req && (((priv_lvl_i == riscv::PRIV_LVL_U) && ~itlb_content[0].u)
|| ((priv_lvl_i == riscv::PRIV_LVL_S) && itlb_content[0].u));
iaccess_err = icache_areq_i.fetch_req && (((priv_lvl_i == riscv::PRIV_LVL_U) && ~itlb_content.u)
|| ((priv_lvl_i == riscv::PRIV_LVL_S) && itlb_content.u));

// MMU enabled: address from TLB, request delayed until hit. Error when TLB
// hit and no access right or TLB hit and translated address not valid (e.g.
Expand Down Expand Up @@ -450,11 +444,11 @@ assign lsu_paddr_o [11:0] = lsu_vaddr_q[11:0];
assign lsu_paddr_o [riscv::PLEN-1:PPNWMin+1] =
(en_ld_st_translation_i && !misaligned_ex_q.valid) ? //
dtlb_pte_q.ppn[riscv::PPNW-1:(riscv::PPNW - (riscv::PLEN - PPNWMin-1))] : //
(riscv::PLEN-PPNWMin-1)'(lsu_vaddr_q[((riscv::PLEN > riscv::VLEN) ? riscv::VLEN : riscv::PLEN )-1:PPNWMin+1]);
(riscv::PLEN-PPNWMin)'(lsu_vaddr_q[((riscv::PLEN > riscv::VLEN) ? riscv::VLEN : riscv::PLEN )-1:PPNWMin+1]);

assign lsu_dtlb_ppn_o [11:0] =
(en_ld_st_translation_i && !misaligned_ex_q.valid) ? //
dtlb_content[0].ppn[11:0] : //
dtlb_content.ppn[11:0] : //
lsu_vaddr_n[23:12];

genvar i;
Expand All @@ -468,22 +462,22 @@ genvar i;

assign lsu_dtlb_ppn_o[PPNWMin-((VPN_LEN/PT_LEVELS)*(i)):PPNWMin-((VPN_LEN/PT_LEVELS)*(i+1))+1] = //
(en_ld_st_translation_i && !misaligned_ex_q.valid && (|dtlb_is_page_q[i:0]==0)) ? //
dtlb_content[0].ppn[PPNWMin-((VPN_LEN/PT_LEVELS)*(i)):PPNWMin-((VPN_LEN/PT_LEVELS)*(i+1))+1] : //
dtlb_content.ppn[PPNWMin-((VPN_LEN/PT_LEVELS)*(i)):PPNWMin-((VPN_LEN/PT_LEVELS)*(i+1))+1] : //
(en_ld_st_translation_i && !misaligned_ex_q.valid && (|dtlb_is_page_q[i:0]!=0)?
lsu_vaddr_n[PPNWMin-((VPN_LEN/PT_LEVELS)*(i)):PPNWMin-((VPN_LEN/PT_LEVELS)*(i+1))+1]://
(VPN_LEN/PT_LEVELS)'(lsu_vaddr_n[((riscv::PLEN > riscv::VLEN) ? riscv::VLEN -1 : (24 + (VPN_LEN/PT_LEVELS)*(PT_LEVELS-i-1) ) -1): (riscv::PLEN > riscv::VLEN) ? 24 :24 + (VPN_LEN/PT_LEVELS)*(PT_LEVELS-i-2)]));
end
if(riscv::IS_XLEN64) begin
assign lsu_dtlb_ppn_o[riscv::PPNW-1:PPNWMin+1] = (en_ld_st_translation_i && !misaligned_ex_q.valid) ?
dtlb_content[0].ppn[riscv::PPNW-1:PPNWMin+1] :
dtlb_content.ppn[riscv::PPNW-1:PPNWMin+1] :
lsu_vaddr_n[riscv::PLEN-1:PPNWMin+1] ;
end

endgenerate
// The data interface is simpler and only consists of a request/response interface
always_comb begin : data_interface
// save request and DTLB response
lsu_vaddr_n = lsu_vaddr_i[0];
lsu_vaddr_n = lsu_vaddr_i;
lsu_req_n = lsu_req_i;
misaligned_ex_n = misaligned_ex_i;
dtlb_pte_n = dtlb_content;
Expand Down
4 changes: 2 additions & 2 deletions core/mmu_unify/cva6_ptw.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -141,7 +141,7 @@ genvar x;
for (x=0; x < PT_LEVELS-1; x++) begin

// update the correct page table level
assign shared_tlb_update_o.is_page[0][x] = (ptw_lvl_q == (x));
assign shared_tlb_update_o.is_page[x] = (ptw_lvl_q == (x));

// check if the ppn is correctly aligned:
// 6. If i > 0 and pa.ppn[i − 1 : 0] != 0, this is a misaligned superpage; stop and raise a page-fault
Expand All @@ -157,7 +157,7 @@ genvar x;


// output the correct ASID
assign shared_tlb_update_o.asid[0] = tlb_update_asid_q;
assign shared_tlb_update_o.asid = tlb_update_asid_q;
// set the global mapping bit
assign shared_tlb_update_o.content = pte | (global_mapping_q << 5);

Expand Down
14 changes: 7 additions & 7 deletions core/mmu_unify/cva6_shared_tlb.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -237,14 +237,14 @@ module cva6_shared_tlb
if (itlb_req_q) begin
itlb_update_o.valid = 1'b1;
itlb_update_o.vpn = itlb_vpn_q;
itlb_update_o.is_page[0] = shared_tag_rd[i].is_page;
itlb_update_o.asid[0] = tlb_update_asid_q;
itlb_update_o.is_page = shared_tag_rd[i].is_page;
itlb_update_o.asid = tlb_update_asid_q;
itlb_update_o.content = pte[i];
end else if (dtlb_req_q) begin
dtlb_update_o.valid = 1'b1;
dtlb_update_o.vpn = dtlb_vpn_q;
dtlb_update_o.is_page[0] = shared_tag_rd[i].is_page;
dtlb_update_o.asid[0] = tlb_update_asid_q;
dtlb_update_o.is_page = shared_tag_rd[i].is_page;
dtlb_update_o.asid = tlb_update_asid_q;
dtlb_update_o.content = pte[i];
end
end
Expand Down Expand Up @@ -300,10 +300,10 @@ module cva6_shared_tlb
end
end //update_flush

assign shared_tag_wr.asid = shared_tlb_update_i.asid[0];
assign shared_tag_wr.asid = shared_tlb_update_i.asid;
// assign shared_tag_wr.vpn[1] = shared_tlb_update_i.vpn[19:10];
// assign shared_tag_wr.vpn[0] = shared_tlb_update_i.vpn[9:0];
assign shared_tag_wr.is_page = shared_tlb_update_i.is_page[0];
assign shared_tag_wr.is_page = shared_tlb_update_i.is_page;


genvar z;
Expand All @@ -318,7 +318,7 @@ module cva6_shared_tlb
assign tag_wr_data = shared_tag_wr;

assign pte_wr_addr = shared_tlb_update_i.vpn[$clog2(SHARED_TLB_DEPTH)-1:0];
assign pte_wr_data = shared_tlb_update_i.content[0];
assign pte_wr_data = shared_tlb_update_i.content;

assign way_valid = shared_tag_valid_q[shared_tlb_update_i.vpn[$clog2(SHARED_TLB_DEPTH)-1:0]];
assign repl_way = (all_ways_valid) ? rnd_way : inv_way;
Expand Down
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