Add 1 cycle delay for misaligned exception and valid translation

core/load_store_unit.sv

@@ -327,17 +327,18 @@ module load_store_unit
     // Delay of 1 cycle to match MMU latency giving the address tag
     always_ff @(posedge clk_i or negedge rst_ni) begin
       if (~rst_ni) begin
-        lsu_paddr <= 'h0;
+        lsu_paddr <= '0;
+        pmp_exception <= '0;
       end else begin
         if (CVA6Cfg.VLEN >= CVA6Cfg.PLEN) begin : gen_virtual_physical_address_lsu
           lsu_paddr <= mmu_vaddr[CVA6Cfg.PLEN-1:0];
         end else begin
           lsu_paddr <= CVA6Cfg.PLEN'(mmu_vaddr);
         end
+        pmp_exception <= misaligned_exception;
+        pmp_translation_valid <= translation_req;
       end
     end
-    assign pmp_exception                       = misaligned_exception;
-    assign pmp_translation_valid               = translation_req;
 
     // dcache interface of PTW not used
     assign dcache_req_ports_o[0].address_index = '0;