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zbkb enabled only in 2 configs
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@munailwaqar
munailwaqar committed Dec 10, 2024
1 parent f63b517 commit cf404bf
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Showing 8 changed files with 32 additions and 28 deletions.
4 changes: 2 additions & 2 deletions core/alu.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -395,8 +395,8 @@ module alu
default: ;
endcase
if (fu_data_i.operation == PACK_W && CVA6Cfg.IS_XLEN64)
result_o = {
{32{fu_data_i.operand_b[15]}}, {fu_data_i.operand_b[15:0]}, {fu_data_i.operand_a[15:0]}
result_o = {
{32{fu_data_i.operand_b[15]}}, {fu_data_i.operand_b[15:0]}, {fu_data_i.operand_a[15:0]}
};
if (fu_data_i.operation == UNZIP && CVA6Cfg.IS_XLEN32) result_o = unzip_gen;
if (fu_data_i.operation == ZIP && CVA6Cfg.IS_XLEN32) result_o = zip_gen;
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29 changes: 14 additions & 15 deletions core/decoder.sv
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Expand Up @@ -779,13 +779,13 @@ module decoder
// Packing
{
7'b000_0100, 3'b100
} :
} :
if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK;
else illegal_instr_bm = 1'b1; //pack
{
7'b000_0100, 3'b111
} :
if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_H;
} :
if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_H;
else illegal_instr_bm = 1'b1; //packh
// Zero Extend Op RV32 encoding
{
Expand Down Expand Up @@ -854,27 +854,26 @@ module decoder
instr.rtype.funct7, instr.rtype.funct3
})
// Shift with Add (Unsigned Word)
{7'b001_0000, 3'b010}: instruction_o.op = ariane_pkg::SH1ADDUW; // sh1add.uw
{7'b001_0000, 3'b100}: instruction_o.op = ariane_pkg::SH2ADDUW; // sh2add.uw
{7'b001_0000, 3'b110}: instruction_o.op = ariane_pkg::SH3ADDUW; // sh3add.uw
{7'b001_0000, 3'b010} : instruction_o.op = ariane_pkg::SH1ADDUW; // sh1add.uw
{7'b001_0000, 3'b100} : instruction_o.op = ariane_pkg::SH2ADDUW; // sh2add.uw
{7'b001_0000, 3'b110} : instruction_o.op = ariane_pkg::SH3ADDUW; // sh3add.uw
// Unsigned word Op's
{7'b000_0100, 3'b000}: instruction_o.op = ariane_pkg::ADDUW; // add.uw
{7'b000_0100, 3'b000} : instruction_o.op = ariane_pkg::ADDUW; // add.uw
// Bitwise Shifting
{7'b011_0000, 3'b001} : instruction_o.op = ariane_pkg::ROLW; // rolw
{7'b011_0000, 3'b101} : instruction_o.op = ariane_pkg::RORW; // rorw
// Pack_W
{
7'b000_0100, 3'b100
} :
if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_W;
} :
if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_W;
else illegal_instr_bm = 1'b1; //packw
// Zero Extend Op RV64 encoding
{7'b000_0100, 3'b100}:
begin
if (instr.instr[24:20] == 5'b00000)
instruction_o.op = ariane_pkg::ZEXTH;
else
illegal_instr_bm = 1'b1;
{
7'b000_0100, 3'b100
} : begin
if (instr.instr[24:20] == 5'b00000) instruction_o.op = ariane_pkg::ZEXTH;
else illegal_instr_bm = 1'b1;
end
default: illegal_instr_bm = 1'b1;
endcase
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6 changes: 4 additions & 2 deletions core/include/build_config_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -124,15 +124,17 @@ package build_config_pkg;
cfg.AxiBurstWriteEn = CVA6Cfg.AxiBurstWriteEn;

cfg.ICACHE_SET_ASSOC = CVA6Cfg.IcacheSetAssoc;
cfg.ICACHE_SET_ASSOC_WIDTH = CVA6Cfg.IcacheSetAssoc > 1 ? $clog2(CVA6Cfg.IcacheSetAssoc) : CVA6Cfg.IcacheSetAssoc;
cfg.ICACHE_SET_ASSOC_WIDTH = CVA6Cfg.IcacheSetAssoc > 1 ? $clog2(CVA6Cfg.IcacheSetAssoc) :
CVA6Cfg.IcacheSetAssoc;
cfg.ICACHE_INDEX_WIDTH = ICACHE_INDEX_WIDTH;
cfg.ICACHE_TAG_WIDTH = cfg.PLEN - ICACHE_INDEX_WIDTH;
cfg.ICACHE_LINE_WIDTH = CVA6Cfg.IcacheLineWidth;
cfg.ICACHE_USER_LINE_WIDTH = (CVA6Cfg.AxiUserWidth == 1) ? 4 : CVA6Cfg.IcacheLineWidth;
cfg.DCacheType = CVA6Cfg.DCacheType;
cfg.DcacheIdWidth = CVA6Cfg.DcacheIdWidth;
cfg.DCACHE_SET_ASSOC = CVA6Cfg.DcacheSetAssoc;
cfg.DCACHE_SET_ASSOC_WIDTH = CVA6Cfg.DcacheSetAssoc > 1 ? $clog2(CVA6Cfg.DcacheSetAssoc) : CVA6Cfg.DcacheSetAssoc;
cfg.DCACHE_SET_ASSOC_WIDTH = CVA6Cfg.DcacheSetAssoc > 1 ? $clog2(CVA6Cfg.DcacheSetAssoc) :
CVA6Cfg.DcacheSetAssoc;
cfg.DCACHE_INDEX_WIDTH = DCACHE_INDEX_WIDTH;
cfg.DCACHE_TAG_WIDTH = cfg.PLEN - DCACHE_INDEX_WIDTH;
cfg.DCACHE_LINE_WIDTH = CVA6Cfg.DcacheLineWidth;
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2 changes: 1 addition & 1 deletion core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -91,7 +91,7 @@ package cva6_config_pkg;
XF8: bit'(CVA6ConfigF8En),
RVA: bit'(CVA6ConfigAExtEn),
RVB: bit'(CVA6ConfigBExtEn),
ZKN: bit'(1),
ZKN: bit'(0),
RVV: bit'(CVA6ConfigVExtEn),
RVC: bit'(CVA6ConfigCExtEn),
RVH: bit'(CVA6ConfigHExtEn),
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4 changes: 2 additions & 2 deletions core/include/cv32a6_imac_sv32_config_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ package cva6_config_pkg;
localparam CVA6ConfigZcmpExtEn = 0;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigHExtEn = 0; // always disabled
localparam CVA6ConfigBExtEn = 0;
localparam CVA6ConfigBExtEn = 1;
localparam CVA6ConfigVExtEn = 0;
localparam CVA6ConfigRVZiCond = 0;

Expand Down Expand Up @@ -91,7 +91,7 @@ package cva6_config_pkg;
XF8: bit'(CVA6ConfigF8En),
RVA: bit'(CVA6ConfigAExtEn),
RVB: bit'(CVA6ConfigBExtEn),
ZKN: bit'(0),
ZKN: bit'(1),
RVV: bit'(CVA6ConfigVExtEn),
RVC: bit'(CVA6ConfigCExtEn),
RVH: bit'(CVA6ConfigHExtEn),
Expand Down
2 changes: 1 addition & 1 deletion core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -98,7 +98,7 @@ package cva6_config_pkg;
XF8: bit'(CVA6ConfigF8En),
RVA: bit'(CVA6ConfigAExtEn),
RVB: bit'(CVA6ConfigBExtEn),
ZKN: bit'(1),
ZKN: bit'(0),
RVV: bit'(CVA6ConfigVExtEn),
RVC: bit'(CVA6ConfigCExtEn),
RVH: bit'(CVA6ConfigHExtEn),
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2 changes: 1 addition & 1 deletion core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -91,7 +91,7 @@ package cva6_config_pkg;
XF8: bit'(CVA6ConfigF8En),
RVA: bit'(CVA6ConfigAExtEn),
RVB: bit'(CVA6ConfigBExtEn),
ZKN: bit'(1),
ZKN: bit'(0),
RVV: bit'(CVA6ConfigVExtEn),
RVC: bit'(CVA6ConfigCExtEn),
RVH: bit'(CVA6ConfigHExtEn),
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11 changes: 7 additions & 4 deletions verif/sim/cva6.py
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Original file line number Diff line number Diff line change
Expand Up @@ -877,16 +877,19 @@ def load_config(args, cwd):
if base in ("cv64a6_imafdch_sv39", "cv64a6_imafdch_sv39_wb"):
args.mabi = "lp64d"
args.isa = "rv64gch_zba_zbb_zbs_zbc"
elif base in ("cv64a6_imafdc_sv39", "cv64a6_imafdc_sv39_hpdcache", "cv64a6_imafdc_sv39_wb"):
elif base in ("cv64a6_imafdc_sv39_hpdcache", "cv64a6_imafdc_sv39_wb"):
args.mabi = "lp64d"
args.isa = "rv64gc_zba_zbb_zbs_zbc"
elif base in ("cv64a6_imafdc_sv39"):
args.mabi = "lp64d"
args.isa = "rv64gc_zba_zbb_zbs_zbc_zbkb"
elif base == "cv32a60x":
args.mabi = "ilp32"
args.isa = "rv32imc_zba_zbb_zbs_zbc_zbkb"
args.isa = "rv32imc_zba_zbb_zbs_zbc"
args.priv = "m"
elif base == "cv32a65x":
args.mabi = "ilp32"
args.isa = "rv32imc_zba_zbb_zbs_zbc_zbkb"
args.isa = "rv32imc_zba_zbb_zbs_zbc"
args.priv = "m"
elif base == "cv64a6_mmu":
args.mabi = "lp64"
Expand All @@ -896,7 +899,7 @@ def load_config(args, cwd):
args.isa = "rv32imac"
elif base == "cv32a6_imac_sv32":
args.mabi = "ilp32"
args.isa = "rv32imac"
args.isa = "rv32imac_zbkb"
elif base == "cv32a6_imafc_sv32":
args.mabi = "ilp32f"
args.isa = "rv32imafc"
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