Modify coding style to improve CC (#1672)

openhwgroup · Dec 5, 2023 · cbd3e9f · cbd3e9f
1 parent 3720295
commit cbd3e9f
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Showing 5 changed files with 48 additions and 53 deletions.
diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv
@@ -1341,7 +1341,7 @@ module csr_regfile
         privilege_violation = 1'b1;
       end
       // check access to debug mode only CSRs
-      if (csr_addr_i[11:4] == 8'h7b && !debug_mode_q) begin
+      if ((!CVA6Cfg.DebugEn && csr_addr_i[11:4] == 8'h7b) || (CVA6Cfg.DebugEn && csr_addr_i[11:4] == 8'h7b && !debug_mode_q)) begin
         privilege_violation = 1'b1;
       end
       // check counter-enabled counter CSR accesses

diff --git a/core/decoder.sv b/core/decoder.sv
@@ -201,7 +201,7 @@ module decoder
                   if (instr.instr[31:25] == 7'b1001) begin
                     // check privilege level, SFENCE.VMA can only be executed in M/S mode
                     // otherwise decode an illegal instruction
-                    illegal_instr    = (((CVA6Cfg.RVS && priv_lvl_i == riscv::PRIV_LVL_S) || priv_lvl_i == riscv::PRIV_LVL_M) && instr.itype.rd == '0) ? 1'b0 : 1'b1;
+                    illegal_instr    = (((CVA6Cfg.RVS && priv_lvl_i == riscv::PRIV_LVL_S) || ((!CVA6Cfg.RVS && !CVA6Cfg.RVU) || priv_lvl_i == riscv::PRIV_LVL_M)) && instr.itype.rd == '0) ? 1'b0 : 1'b1;
                     instruction_o.op = ariane_pkg::SFENCE_VMA;
                     // check TVM flag and intercept SFENCE.VMA call if necessary
                     if (CVA6Cfg.RVS && priv_lvl_i == riscv::PRIV_LVL_S && tvm_i)
@@ -1323,12 +1323,13 @@ module decoder
         // this exception is valid
         instruction_o.ex.valid = 1'b1;
         // depending on the privilege mode, set the appropriate cause
-        case (priv_lvl_i)
-          riscv::PRIV_LVL_M: instruction_o.ex.cause = riscv::ENV_CALL_MMODE;
-          riscv::PRIV_LVL_S: if (CVA6Cfg.RVS) instruction_o.ex.cause = riscv::ENV_CALL_SMODE;
-          riscv::PRIV_LVL_U: if (CVA6Cfg.RVU) instruction_o.ex.cause = riscv::ENV_CALL_UMODE;
-          default: ;  // this should not happen
-        endcase
+        if (priv_lvl_i == riscv::PRIV_LVL_M) begin
+          instruction_o.ex.cause = riscv::ENV_CALL_MMODE;
+        end else if (priv_lvl_i == riscv::PRIV_LVL_S && CVA6Cfg.RVS) begin
+          instruction_o.ex.cause = riscv::ENV_CALL_SMODE;
+        end else if (priv_lvl_i == riscv::PRIV_LVL_U && CVA6Cfg.RVU) begin
+          instruction_o.ex.cause = riscv::ENV_CALL_UMODE;
+        end
       end else if (ebreak) begin
         // this exception is valid
         instruction_o.ex.valid = 1'b1;

diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv
@@ -147,13 +147,15 @@ module issue_read_operands
     unique case (issue_instr_i.fu)
       NONE: fu_busy = 1'b0;
       ALU, CTRL_FLOW, CSR, MULT: fu_busy = ~flu_ready_i;
-      FPU, FPU_VEC:
-      if (CVA6Cfg.FpPresent) begin
-        fu_busy = ~fpu_ready_i;
-      end else fu_busy = 1'b0;
       LOAD, STORE: fu_busy = ~lsu_ready_i;
       CVXIF: fu_busy = ~cvxif_ready_i;
-      default: fu_busy = 1'b0;
+      default: begin
+        if (CVA6Cfg.FpPresent && (issue_instr_i.fu == FPU || issue_instr_i.fu == FPU_VEC)) begin
+          fu_busy = ~fpu_ready_i;
+        end else begin
+          fu_busy = 1'b0;
+        end
+      end
     endcase
   end
 
@@ -318,27 +320,23 @@ module issue_read_operands
           MULT: begin
             mult_valid_q <= 1'b1;
           end
-          FPU: begin
-            if (CVA6Cfg.FpPresent) begin
+          LOAD, STORE: begin
+            lsu_valid_q <= 1'b1;
+          end
+          CSR: begin
+            csr_valid_q <= 1'b1;
+          end
+          default: begin
+            if (issue_instr_i.fu == FPU && CVA6Cfg.FpPresent) begin
               fpu_valid_q <= 1'b1;
               fpu_fmt_q   <= orig_instr.rftype.fmt;  // fmt bits from instruction
               fpu_rm_q    <= orig_instr.rftype.rm;  // rm bits from instruction
-            end
-          end
-          FPU_VEC: begin
-            if (CVA6Cfg.FpPresent) begin
+            end else if (issue_instr_i.fu == FPU_VEC && CVA6Cfg.FpPresent) begin
               fpu_valid_q <= 1'b1;
               fpu_fmt_q   <= orig_instr.rvftype.vfmt;  // vfmt bits from instruction
               fpu_rm_q    <= {2'b0, orig_instr.rvftype.repl};  // repl bit from instruction
             end
           end
-          LOAD, STORE: begin
-            lsu_valid_q <= 1'b1;
-          end
-          CSR: begin
-            csr_valid_q <= 1'b1;
-          end
-          default: ;
         endcase
       end
       // if we got a flush request, de-assert the valid flag, otherwise we will start this

diff --git a/core/load_unit.sv b/core/load_unit.sv
@@ -257,27 +257,6 @@ module load_unit
         end
       end
 
-      // abort the previous request - free the D$ arbiter
-      // we are here because of a TLB miss, we need to abort the current request and give way for the
-      // PTW walker to satisfy the TLB miss
-      ABORT_TRANSACTION: begin
-        if (ariane_pkg::MMU_PRESENT) begin
-          req_port_o.kill_req = 1'b1;
-          req_port_o.tag_valid = 1'b1;
-          // wait until the WB is empty
-          state_d = WAIT_TRANSLATION;
-        end
-      end
-
-      ABORT_TRANSACTION_NI: begin
-        if (CVA6Cfg.NonIdemPotenceEn) begin
-          req_port_o.kill_req = 1'b1;
-          req_port_o.tag_valid = 1'b1;
-          // re-do the request
-          state_d = WAIT_WB_EMPTY;
-        end
-      end
-
       // Wait until the write-back buffer is empty in the data cache.
       WAIT_WB_EMPTY: begin
         // the write buffer is empty, so lets go and re-do the translation.
@@ -378,7 +357,24 @@ module load_unit
         state_d = IDLE;
       end
 
-      default: state_d = IDLE;
+      default: begin
+        // abort the previous request - free the D$ arbiter
+        // we are here because of a TLB miss, we need to abort the current request and give way for the
+        // PTW walker to satisfy the TLB miss
+        if (state_q == ABORT_TRANSACTION && ariane_pkg::MMU_PRESENT) begin
+          req_port_o.kill_req = 1'b1;
+          req_port_o.tag_valid = 1'b1;
+          // wait until the WB is empty
+          state_d = WAIT_TRANSLATION;
+        end else if (state_q == ABORT_TRANSACTION_NI && CVA6Cfg.NonIdemPotenceEn) begin
+          req_port_o.kill_req = 1'b1;
+          req_port_o.tag_valid = 1'b1;
+          // re-do the request
+          state_d = WAIT_WB_EMPTY;
+        end else begin
+          state_d = IDLE;
+        end
+      end
     endcase
 
     // if we just flushed and the queue is not empty or we are getting an rvalid this cycle wait in a extra stage

diff --git a/core/store_unit.sv b/core/store_unit.sv
@@ -151,11 +151,11 @@ module store_unit
         end
       end
 
-      // we didn't receive a valid translation, wait for one
-      // but we know that the store queue is not full as we could only have landed here if
-      // it wasn't full
-      WAIT_TRANSLATION: begin
-        if (ariane_pkg::MMU_PRESENT) begin
+      default: begin
+        // we didn't receive a valid translation, wait for one
+        // but we know that the store queue is not full as we could only have landed here if
+        // it wasn't full
+        if (state_q == WAIT_TRANSLATION && ariane_pkg::MMU_PRESENT) begin
           translation_req_o = 1'b1;
 
           if (dtlb_hit_i) begin