Update UART submodule to version 0.2.1 and Use SV UART in vcs-testhar…

…ness (#2196)
openhwgroup · Jun 17, 2024 · c93587b · c93587b
1 parent db08815
commit c93587b
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Showing 2 changed files with 22 additions and 7 deletions.
diff --git a/Makefile b/Makefile
@@ -183,7 +183,7 @@ src :=  $(if $(spike-tandem),verif/tb/core/uvma_core_cntrl_pkg.sv)
         vendor/pulp-platform/common_cells/src/rstgen_bypass.sv                       \
         vendor/pulp-platform/common_cells/src/rstgen.sv                              \
         vendor/pulp-platform/common_cells/src/addr_decode.sv                         \
-	vendor/pulp-platform/common_cells/src/stream_register.sv                     \
+        vendor/pulp-platform/common_cells/src/stream_register.sv                     \
         vendor/pulp-platform/axi/src/axi_cut.sv                                      \
         vendor/pulp-platform/axi/src/axi_join.sv                                     \
         vendor/pulp-platform/axi/src/axi_delayer.sv                                  \
@@ -217,9 +217,24 @@ copro_src := core/cvxif_example/include/cvxif_instr_pkg.sv \
              $(wildcard core/cvxif_example/*.sv)
 copro_src := $(addprefix $(root-dir), $(copro_src))
 
-uart_src := $(wildcard corev_apu/fpga/src/apb_uart/src/*.vhd)
+uart_src := $(wildcard corev_apu/fpga/src/apb_uart/src/vhdl_orig/*.vhd)
 uart_src := $(addprefix $(root-dir), $(uart_src))
 
+uart_src_sv:= corev_apu/fpga/src/apb_uart/src/slib_clock_div.sv     \
+              corev_apu/fpga/src/apb_uart/src/slib_counter.sv       \
+              corev_apu/fpga/src/apb_uart/src/slib_edge_detect.sv   \
+              corev_apu/fpga/src/apb_uart/src/slib_fifo.sv          \
+              corev_apu/fpga/src/apb_uart/src/slib_input_filter.sv  \
+              corev_apu/fpga/src/apb_uart/src/slib_input_sync.sv    \
+              corev_apu/fpga/src/apb_uart/src/slib_mv_filter.sv     \
+              corev_apu/fpga/src/apb_uart/src/uart_baudgen.sv       \
+              corev_apu/fpga/src/apb_uart/src/uart_interrupt.sv     \
+              corev_apu/fpga/src/apb_uart/src/uart_receiver.sv      \
+              corev_apu/fpga/src/apb_uart/src/uart_transmitter.sv   \
+              corev_apu/fpga/src/apb_uart/src/apb_uart.sv           \
+              corev_apu/fpga/src/apb_uart/src/apb_uart_wrap.sv
+uart_src_sv := $(addprefix $(root-dir), $(uart_src_sv))
+
 fpga_src :=  $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/ariane-ethernet/*.sv) common/local/util/tc_sram_fpga_wrapper.sv vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv
 fpga_src := $(addprefix $(root-dir), $(fpga_src)) src/bootrom/bootrom_$(XLEN).sv
 
@@ -307,7 +322,7 @@ vcs_build: $(dpi-library)/ariane_dpi.so
 	cd $(vcs-library) &&\
 	vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog +define+$(defines) -assert svaext -f $(flist) $(list_incdir) ../corev_apu/tb/common/mock_uart.sv -timescale=1ns/1ns &&\
 	vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog +define+$(defines) $(filter %.sv,$(ariane_pkg)) +incdir+core/include/+$(VCS_HOME)/etc/uvm-1.2/dpi &&\
-	vhdlan $(if $(VERDI), -kdb,) -full64 -nc $(filter %.vhd,$(uart_src)) &&\
+	vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog $(uart_src_sv) &&\
 	vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -assert svaext +define+$(defines) +incdir+$(VCS_HOME)/etc/uvm/src $(VCS_HOME)/etc/uvm/src/uvm_pkg.sv  $(filter %.sv,$(src)) $(list_incdir) &&\
 	vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 &&\
 	vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 $(tbs) +define+$(defines) $(list_incdir) &&\
@@ -453,7 +468,7 @@ XRUN_COMP_FLAGS  ?= -64bit -v200x -disable_sem2009 -access +rwc 			\
 		    -smartorder -sv -top worklib.$(top_level)			\
 		    -timescale 1ns/1ps
 
-XRUN_RUN_FLAGS := -R -messages -status -64bit -licqueue -noupdate -uvmhome CDNS-1.2 -sv_lib $(CVA6_HOME)/$(dpi-library)/xrun_ariane_dpi.so +UVM_VERBOSITY=UVM_LOW  		
+XRUN_RUN_FLAGS := -R -messages -status -64bit -licqueue -noupdate -uvmhome CDNS-1.2 -sv_lib $(CVA6_HOME)/$(dpi-library)/xrun_ariane_dpi.so +UVM_VERBOSITY=UVM_LOW
 
 XRUN_DISABLED_WARNINGS := BIGWIX 	\
 			ZROMCW 		\
@@ -471,10 +486,10 @@ XRUN_COMP = $(XRUN_COMP_FLAGS)		\
 	$(filter %.sv, $(ariane_pkg)) 	\
 	$(filter %.sv, $(src))	      	\
 	$(filter %.vhd, $(uart_src))  	\
-	$(filter %.sv, $(XRUN_TB))	
+	$(filter %.sv, $(XRUN_TB))
 
 XRUN_RUN = $(XRUN_RUN_FLAGS) 		\
-	$(XRUN_DISABLED_WARNINGS)	
+	$(XRUN_DISABLED_WARNINGS)
 
 xrun_clean:
 	@echo "[XRUN] clean up"

diff --git a/corev_apu/fpga/src/apb_uart b/corev_apu/fpga/src/apb_uart
+22 −13		Bender.yml
+15 −1		CHANGELOG.md
+948 −0		src/apb_uart.sv
+76 −0		src/apb_uart_wrap.sv
+100 −0		src/reg_uart_wrap.sv
+75 −0		src/slib_clock_div.sv
+88 −0		src/slib_counter.sv
+62 −0		src/slib_edge_detect.sv
+159 −0		src/slib_fifo.sv
+81 −0		src/slib_input_filter.sv
+60 −0		src/slib_input_sync.sv
+78 −0		src/slib_mv_filter.sv
+78 −0		src/uart_baudgen.sv
+98 −0		src/uart_interrupt.sv
+315 −0		src/uart_receiver.sv
+320 −0		src/uart_transmitter.sv
+2 −4		src/vhdl_orig/apb_uart.vhd
+0 −0		src/vhdl_orig/slib_clock_div.vhd
+0 −0		src/vhdl_orig/slib_counter.vhd
+0 −0		src/vhdl_orig/slib_edge_detect.vhd
+0 −0		src/vhdl_orig/slib_fifo.vhd
+0 −0		src/vhdl_orig/slib_input_filter.vhd
+0 −0		src/vhdl_orig/slib_input_sync.vhd
+0 −0		src/vhdl_orig/slib_mv_filter.vhd
+3 −3		src/vhdl_orig/uart_baudgen.vhd
+0 −0		src/vhdl_orig/uart_interrupt.vhd
+0 −0		src/vhdl_orig/uart_receiver.vhd
+0 −0		src/vhdl_orig/uart_transmitter.vhd
+14 −12		src_files.yml
+36 −0		util/equiv_check.fm.tcl