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Enable reads on CSR_HPM_COUNTERx (#1824)
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luca-valente authored Feb 21, 2024
1 parent 5dd0482 commit c84f979
Showing 1 changed file with 19 additions and 0 deletions.
19 changes: 19 additions & 0 deletions core/perf_counters.sv
Original file line number Diff line number Diff line change
Expand Up @@ -174,6 +174,25 @@ module perf_counters
riscv::CSR_MHPM_EVENT_7,
riscv::CSR_MHPM_EVENT_8 :
data_o = mhpmevent_q[addr_i-riscv::CSR_MHPM_EVENT_3+1];
riscv::CSR_HPM_COUNTER_3,
riscv::CSR_HPM_COUNTER_4,
riscv::CSR_HPM_COUNTER_5,
riscv::CSR_HPM_COUNTER_6,
riscv::CSR_HPM_COUNTER_7,
riscv::CSR_HPM_COUNTER_8 :begin
if (riscv::XLEN == 32) data_o = generic_counter_q[addr_i-riscv::CSR_HPM_COUNTER_3+1][31:0];
else data_o = generic_counter_q[addr_i-riscv::CSR_HPM_COUNTER_3+1];
end
riscv::CSR_HPM_COUNTER_3H,
riscv::CSR_HPM_COUNTER_4H,
riscv::CSR_HPM_COUNTER_5H,
riscv::CSR_HPM_COUNTER_6H,
riscv::CSR_HPM_COUNTER_7H,
riscv::CSR_HPM_COUNTER_8H :begin
if (riscv::XLEN == 32)
data_o = generic_counter_q[addr_i-riscv::CSR_HPM_COUNTER_3H+1][63:32];
else read_access_exception = 1'b1;
end
default: data_o = 'b0;
endcase

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