Add the condition for updating the tlb only after a miss is incurred (#…

…2120)
openhwgroup · May 23, 2024 · be14a84 · be14a84
1 parent f8b07f0
commit be14a84
Showing 1 changed file with 1 addition and 2 deletions.
diff --git a/core/cva6_mmu/cva6_tlb.sv b/core/cva6_mmu/cva6_tlb.sv
@@ -285,8 +285,7 @@ module cva6_tlb
             tags_n[i].valid = 1'b0;
         end
         // normal replacement
-      end else if (update_i.valid & replace_en[i]) begin
-        // end else if (update_i.valid & replace_en[i] && !lu_hit_o) begin //to add this fix
+      end else if (update_i.valid & replace_en[i] & !lu_hit_o) begin
         //update tag
         tags_n[i] = {
           update_i.asid,