Re-factor halt and exception address as parameter

Bender.yml

@@ -25,7 +25,6 @@ sources:
         files:
           - core/include/cv64a6_imafdcv_sv39_config_pkg.sv
           - core/include/riscv_pkg.sv
-          - core/include/ariane_dm_pkg.sv
           - core/include/ariane_pkg.sv
           - core/mmu_sv39/tlb.sv
           - core/mmu_sv39/mmu.sv
@@ -36,7 +35,6 @@ sources:
         files:
           - core/include/cv64a6_imafdc_sv39_config_pkg.sv
           - core/include/riscv_pkg.sv
-          - core/include/ariane_dm_pkg.sv
           - core/include/ariane_pkg.sv
           - core/mmu_sv39/tlb.sv
           - core/mmu_sv39/mmu.sv
@@ -47,7 +45,6 @@ sources:
         files:
           - core/include/cv32a6_imac_sv0_config_pkg.sv
           - core/include/riscv_pkg.sv
-          - core/include/ariane_dm_pkg.sv
           - core/include/ariane_pkg.sv
           - core/mmu_sv32/cva6_tlb_sv32.sv
           - core/mmu_sv32/cva6_mmu_sv32.sv
@@ -58,7 +55,6 @@ sources:
         files:
           - core/include/cv32a6_imac_sv32_config_pkg.sv
           - core/include/riscv_pkg.sv
-          - core/include/ariane_dm_pkg.sv
           - core/include/ariane_pkg.sv
           - core/mmu_sv32/cva6_tlb_sv32.sv
           - core/mmu_sv32/cva6_mmu_sv32.sv
@@ -69,7 +65,6 @@ sources:
         files:
           - core/include/cv32a6_imafc_sv32_config_pkg.sv
           - core/include/riscv_pkg.sv
-          - core/include/ariane_dm_pkg.sv
           - core/include/ariane_pkg.sv
           - core/mmu_sv32/cva6_tlb_sv32.sv
           - core/mmu_sv32/cva6_mmu_sv32.sv

Flist.ariane

@@ -22,7 +22,6 @@
 core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
 core/include/riscv_pkg.sv
 corev_apu/riscv-dbg/src/dm_pkg.sv
-core/include/ariane_dm_pkg.sv
 vendor/openhwgroup/cvfpu/src/fpnew_pkg.sv
 core/include/ariane_pkg.sv
 core/include/acc_pkg.sv

core/Flist.cva6

@@ -58,7 +58,6 @@ ${CVA6_REPO_DIR}/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mv
 ${CVA6_REPO_DIR}/core/include/config_pkg.sv
 ${CVA6_REPO_DIR}/core/include/${TARGET_CFG}_config_pkg.sv
 ${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
-${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv
 // Note: depends on fpnew_pkg, above
 ${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/axi/src/axi_pkg.sv

core/Flist.cva6_gate

@@ -11,7 +11,6 @@
 ${CVA6_REPO_DIR}/core/include/config_pkg.sv
 ${CVA6_REPO_DIR}/core/include/${TARGET_CFG}_config_pkg.sv
 ${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
-${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv
 ${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/axi/src/axi_pkg.sv
 

core/csr_regfile.sv

@@ -1034,7 +1034,7 @@ module csr_regfile import ariane_pkg::*; #(
                 endcase
                 // save PC of next this instruction e.g.: the next one to be executed
                 dpc_d = {{riscv::XLEN-riscv::VLEN{pc_i[riscv::VLEN-1]}},pc_i};
-                dcsr_d.cause = ariane_dm_pkg::CauseBreakpoint;
+                dcsr_d.cause = ariane_pkg::CauseBreakpoint;
             end
 
             // we've got a debug request
@@ -1047,7 +1047,7 @@ module csr_regfile import ariane_pkg::*; #(
                 // jump to the base address
                 set_debug_pc_o = 1'b1;
                 // save the cause as external debug request
-                dcsr_d.cause = ariane_dm_pkg::CauseRequest;
+                dcsr_d.cause = ariane_pkg::CauseRequest;
             end
 
             // single step enable and we just retired an instruction
@@ -1069,7 +1069,7 @@ module csr_regfile import ariane_pkg::*; #(
                 end
                 debug_mode_d = 1'b1;
                 set_debug_pc_o = 1'b1;
-                dcsr_d.cause = ariane_dm_pkg::CauseSingleStep;
+                dcsr_d.cause = ariane_pkg::CauseSingleStep;
             end
         end
         // go in halt-state again when we encounter an exception
@@ -1266,7 +1266,7 @@ module csr_regfile import ariane_pkg::*; #(
 
         // if we are in debug mode jump to a specific address
         if (debug_mode_q) begin
-            trap_vector_base_o = DmBaseAddress[riscv::VLEN-1:0] + ariane_dm_pkg::ExceptionAddress[riscv::VLEN-1:0];
+            trap_vector_base_o = DmBaseAddress[riscv::VLEN-1:0] + CVA6Cfg.ExceptionAddress[riscv::VLEN-1:0];
         end
 
         // check if we are in vectored mode, if yes then do BASE + 4 * cause we

core/cva6.sv

@@ -190,7 +190,9 @@ module cva6 import ariane_pkg::*; #(
     bit'(XF8Vec),
     unsigned'(NrRgprPorts),
     unsigned'(NrWbPorts),
-    bit'(EnableAccelerator)
+    bit'(EnableAccelerator),
+    CVA6Cfg.HaltAddress,
+    CVA6Cfg.ExceptionAddress
   };
 
 

core/frontend/frontend.sv

@@ -354,7 +354,7 @@ module frontend import ariane_pkg::*; #(
       end
       // 7. Debug
       // enter debug on a hard-coded base-address
-      if (set_debug_pc_i) npc_d = ArianeCfg.DmBaseAddress[riscv::VLEN-1:0] + ariane_dm_pkg::HaltAddress[riscv::VLEN-1:0];
+      if (set_debug_pc_i) npc_d = ArianeCfg.DmBaseAddress[riscv::VLEN-1:0] + CVA6Cfg.HaltAddress[riscv::VLEN-1:0];
       icache_dreq_o.vaddr = fetch_address;
     end
 

core/include/ariane_pkg.sv

@@ -166,13 +166,33 @@ package ariane_pkg;
     localparam NR_RGPR_PORTS = 2;
 
     // static debug hartinfo
-    localparam ariane_dm_pkg::hartinfo_t DebugHartInfo = '{
+    // debug causes
+    localparam logic [2:0] CauseBreakpoint = 3'h1;
+    localparam logic [2:0] CauseTrigger    = 3'h2;
+    localparam logic [2:0] CauseRequest    = 3'h3;
+    localparam logic [2:0] CauseSingleStep = 3'h4;
+    // amount of data count registers implemented
+    localparam logic [3:0] DataCount     = 4'h2;
+
+    // address where data0-15 is shadowed or if shadowed in a CSR
+    // address of the first CSR used for shadowing the data
+    localparam logic [11:0] DataAddr = 12'h380; // we are aligned with Rocket here
+    typedef struct packed {
+      logic [31:24] zero1;
+      logic [23:20] nscratch;
+      logic [19:17] zero0;
+      logic         dataaccess;
+      logic [15:12] datasize;
+      logic [11:0]  dataaddr;
+    } hartinfo_t;
+
+    localparam hartinfo_t DebugHartInfo = '{
                                                 zero1:        '0,
                                                 nscratch:      2, // Debug module needs at least two scratch regs
                                                 zero0:        '0,
                                                 dataaccess: 1'b1, // data registers are memory mapped in the debugger
-                                                datasize: ariane_dm_pkg::DataCount,
-                                                dataaddr: ariane_dm_pkg::DataAddr
+                                                datasize: DataCount,
+                                                dataaddr: DataAddr
                                               };
 
     // enables a commit log which matches spikes commit log format for easier trace comparison

core/include/config_pkg.sv

@@ -44,6 +44,10 @@ package config_pkg;
       int unsigned NrRgprPorts;
       int unsigned NrWbPorts;
       bit EnableAccelerator;
+      // Debug Module
+      // address to which a hart should jump when it was requested to halt
+      logic [63:0] HaltAddress;
+      logic [63:0] ExceptionAddress;
     } cva6_cfg_t;
 
     localparam cva6_cfg_t cva6_cfg_default = {
@@ -74,7 +78,9 @@ package config_pkg;
       bit'(0),           // XF8Vec
       unsigned'(0),      // NrRgprPorts
       unsigned'(0),      // NrWbPorts
-      bit'(0)            // EnableAccelerator
+      bit'(0),           // EnableAccelerator
+      64'h804,           // HaltAddress
+      64'h808            // ExceptionAddress
     } ;
 
     localparam cva6_cfg_t cva6_cfg_empty = {
@@ -105,7 +111,9 @@ package config_pkg;
       bit'(0),           // XF8Vec
       unsigned'(0),      // NrRgprPorts
       unsigned'(0),      // NrWbPorts
-      bit'(0)            // EnableAccelerator
+      bit'(0),           // EnableAccelerator
+      64'h0,             // HaltAddress
+      64'h0              // ExceptionAddress
     } ;
 
 

core/include/cv64a6_imafdc_sv39_config_pkg.sv

@@ -103,7 +103,9 @@ package cva6_config_pkg;
       bit'(0),           // XF8Vec
       unsigned'(0),      // NrRgprPorts
       unsigned'(0),      // NrWbPorts
-      bit'(0)            // EnableAccelerator
+      bit'(0),           // EnableAccelerator
+      64'h804,           // HaltAddress
+      64'h808            // ExceptionAddress            // EnableAccelerator
     } ;
 
 endpackage

util/config_pkg_generator.py

@@ -103,6 +103,10 @@ def setup_parser_config_generator():
                       help="Cache type (WB or WT)")
   parser.add_argument("--MmuPresent", type=int, default=None, choices=[0, 1],
                       help="Use an MMU ? 1 : enable, 0 : disable")
+  parser.add_argument("--HaltAddress", type=int, default=0x804,
+                      help="Address which the core should jump in case of a debug request.")
+  parser.add_argument("--ExceptionAddress", type=int, default=0x808,
+                      help="Address which the core should jump in case of an exception during debug mode.")
   parser.add_argument("--RvfiTrace", type=int, default=None, choices=[0, 1],
                       help="Output an RVFI trace ? 1 : enable, 0 : disable")
   return parser
@@ -156,6 +160,8 @@ def setup_parser_config_generator():
   "MmuPresent": "CVA6ConfigMmuPresent",
   # Ignored parameters
   "ignored": "CVA6ConfigRvfiTrace",
+  "HaltAddress": "CVA6HaltAddress",
+  "ExceptionAddress": "CVA6ExceptionAddress",
 }
 MapParametersToArgs = {i:k for k, i in MapArgsToParameter.items()} #reverse map