Skip to content

Commit

Permalink
suggested format and config changes
Browse files Browse the repository at this point in the history
  • Loading branch information
@munailwaqar
munailwaqar committed Dec 9, 2024
1 parent 030af2d commit ae24f11
Show file tree
Hide file tree
Showing 23 changed files with 41 additions and 122 deletions.
13 changes: 0 additions & 13 deletions config/gen_from_riscv_config/cv32a65x/isa/isa.adoc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -221,16 +221,3 @@
| BSET | bset rd, rs1, rs2 | X(rd) = X(rs1) \| (1 << (X(rs2) & (XLEN - 1))) | NONE | NONE | This instruction returns rs1 with a single bit set at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2. | Single_bit_Operations
| BSETI | bseti rd, rs1, shamt | X(rd) = X(rs1) \| (1 << (shamt & (XLEN - 1))) | NONE | NONE | This instruction returns rs1 with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved. | Single_bit_Operations
|===
==== RVZbkb Bitmanip instructions for Cryptography
|===
| Name | Format | Pseudocode|Invalid_values | Exception_raised | Description| Op Name
| PACK | pack rd, rs1, rs2 | X(rd) = X(rs2)[XLEN/2-1..0] @ X(rs1)[XLEN/2-1..0] | NONE | NONE | This instruction packs the lower halves of rs1 and rs2 into rd, with rs1 in the lower half and rs2 in the upper half. | Pack instructions
| PACKH | packh rd, rs1, rs2 | X(rd) = EXTZ(X(rs2)[7..0] @ X(rs1)[7..0]) | NONE | NONE | This instruction packs the least-significant bytes of rs1 and rs2 into the 16 least-significant bits of rd, zero extending the rest of rd. | Pack instructions
| PACKW | packw rd, rs1, rs2 | X(rd) = EXTS(X(rs2)[15..0] @ X(rs1)[15..0]) | NONE | NONE | This instruction packs the low 16 bits of rs1 and rs2 into the 32 least-significant bits of rd, sign extending the 32-bit result to the rest of rd. | Pack instructions
| ZIP | zip rd, rs | foreach (i from 0 to 15) { X(rd)[i << 1] = X(rs1)[i]; X(rd)[i+1 << 1] = X(rs1)[i+16];} | NONE | NONE | This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction. | Zip instructions
| UNZIP | unzip rd, rs | foreach (i from 0 to 15) { X(rd)[i] = X(rs1)[i << 1]; X(rd)[i+16] = X(rs1)[i+1 << 1];} | NONE | NONE | This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction. | Zip instructions
| BREV8 | brev8 rd, rs | foreach (i from 0 to xlen by 8) {foreach (j from 0 to 7) { X(rd)[(i<<3)+j] = X(rs)[(i<<3)+(7-j)];}} | NONE | NONE | This instruction reverses the order of the bits in every byte of a register. | Bits-in-Byte-reverse
|===
20 changes: 0 additions & 20 deletions config/gen_from_riscv_config/cv32a65x/isa/isa.rst
View file
Original file line number Diff line number Diff line change
Expand Up @@ -395,23 +395,3 @@ RVZbs Single bit Instructions
+--------+----------------------+------------------------------------------------+------------------+--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------+
| BSETI | bseti rd, rs1, shamt | X(rd) = X(rs1) | (1 << (shamt & (XLEN - 1))) | NONE | NONE | This instruction returns rs1 with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved. | Single_bit_Operations |
+--------+----------------------+------------------------------------------------+------------------+--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------+

RVZbkb Bitmanip instructions for Cryptography
-------------------------------------


+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
| Name | Format | Pseudocode | Invalid_values | Exception_raised | Description | Op Name |
+===========+========================+==========================================+==================+====================+===========================================================================================================================================================================================================================+==========================================================================================================================+
| PACK | pack rd, rs1, rs2 | X(rd) = X(rs2)[XLEN/2-1..0] @ X(rs1)[XLEN/2-1..0] | NONE | NONE | This instruction packs the lower halves of rs1 and rs2 into rd, with rs1 in the lower half and rs2 in the upper half. | Pack instructions |
+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
| PACKH | packh rd, rs1, rs2 | X(rd) = EXTZ(X(rs2)[7..0] @ X(rs1)[7..0]) | NONE | NONE | This instruction packs the least-significant bytes of rs1 and rs2 into the 16 least-significant bits of rd, zero extending the rest of rd. | Pack instructions |
+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
| PACKW | packw rd, rs1, rs2 | X(rd) = EXTS(X(rs2)[15..0] @ X(rs1)[15..0]) | NONE | NONE | This instruction packs the low 16 bits of rs1 and rs2 into the 32 least-significant bits of rd, sign extending the 32-bit result to the rest of rd. | Pack instructions |
+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
| ZIP | zip rd, rs | foreach (i from 0 to 15) { X(rd)[i << 1] = X(rs1)[i]; X(rd)[i+1 << 1] = X(rs1)[i+16];} | NONE | NONE | This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction. | Zip instructions |
+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
| UNZIP | unzip rd, rs | foreach (i from 0 to 15) { X(rd)[i] = X(rs1)[i << 1]; X(rd)[i+16] = X(rs1)[i+1 << 1];} | NONE | NONE | This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction. | Zip instructions |
+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
| BREV8 | brev8 rd, rs | foreach (i from 0 to xlen by 8) {foreach (j from 0 to 7) { X(rd)[(i<<3)+j] = X(rs)[(i<<3)+(7-j)];}} | NONE | NONE | This instruction reverses the order of the bits in every byte of a register. | Bits-in-Byte-reverse |
+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
11 changes: 8 additions & 3 deletions core/alu.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -387,12 +387,17 @@ module alu
// ZKN instructions
if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin
unique case (fu_data_i.operation)
PACK: result_o = (CVA6Cfg.IS_XLEN32) ? ({fu_data_i.operand_b[15:0], fu_data_i.operand_a[15:0]}) : ({fu_data_i.operand_b[31:0], fu_data_i.operand_a[31:0]});
PACK_H: result_o = (CVA6Cfg.IS_XLEN32) ? ({16'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]}) : ({48'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]});
PACK:
result_o = (CVA6Cfg.IS_XLEN32) ? ({fu_data_i.operand_b[15:0], fu_data_i.operand_a[15:0]}) : ({fu_data_i.operand_b[31:0], fu_data_i.operand_a[31:0]});
PACK_H:
result_o = (CVA6Cfg.IS_XLEN32) ? ({16'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]}) : ({48'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]});
BREV8: result_o = brev8_reversed;
default: ;
endcase
if (fu_data_i.operation == PACK_W && CVA6Cfg.IS_XLEN64) result_o = {{32{fu_data_i.operand_b[15]}}, {fu_data_i.operand_b[15:0]}, {fu_data_i.operand_a[15:0]}};
if (fu_data_i.operation == PACK_W && CVA6Cfg.IS_XLEN64)
result_o = {
{32{fu_data_i.operand_b[15]}}, {fu_data_i.operand_b[15:0]}, {fu_data_i.operand_a[15:0]}
};
if (fu_data_i.operation == UNZIP && CVA6Cfg.IS_XLEN32) result_o = unzip_gen;
if (fu_data_i.operation == ZIP && CVA6Cfg.IS_XLEN32) result_o = zip_gen;
end
Expand Down
22 changes: 17 additions & 5 deletions core/decoder.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -777,8 +777,16 @@ module decoder
{7'b011_0000, 3'b001} : instruction_o.op = ariane_pkg::ROL; // rol
{7'b011_0000, 3'b101} : instruction_o.op = ariane_pkg::ROR; // ror
// Packing
{7'b000_0100, 3'b100} : if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK; else illegal_instr_bm = 1'b1; //pack
{7'b000_0100, 3'b111} : if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_H; else illegal_instr_bm = 1'b1; //packh
{
7'b000_0100, 3'b100
} :
if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK;
else illegal_instr_bm = 1'b1; //pack
{
7'b000_0100, 3'b111
} :
if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_H;
else illegal_instr_bm = 1'b1; //packh
// Zero Extend Op RV32 encoding
{
7'b000_0100, 3'b100
Expand Down Expand Up @@ -852,10 +860,14 @@ module decoder
// Unsigned word Op's
{7'b000_0100, 3'b000}: instruction_o.op = ariane_pkg::ADDUW; // add.uw
// Bitwise Shifting
{7'b011_0000, 3'b001}: instruction_o.op = ariane_pkg::ROLW; // rolw
{7'b011_0000, 3'b101}: instruction_o.op = ariane_pkg::RORW; // rorw
{7'b011_0000, 3'b001} : instruction_o.op = ariane_pkg::ROLW; // rolw
{7'b011_0000, 3'b101} : instruction_o.op = ariane_pkg::RORW; // rorw
// Pack_W
{7'b000_0100, 3'b100}: if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_W; else illegal_instr_bm = 1'b1; //packw
{
7'b000_0100, 3'b100
} :
if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_W;
else illegal_instr_bm = 1'b1; //packw
// Zero Extend Op RV64 encoding
{7'b000_0100, 3'b100}:

Check warning on line 872 in core/decoder.sv

View workflow job for this annotation

GitHub Actions / format 

[verible-verilog-format] reported by reviewdog 🐶


Raw Output:
core/decoder.sv:872:-                {7'b000_0100, 3'b100}:
core/decoder.sv:873:-                begin
core/decoder.sv:874:-                  if (instr.instr[24:20] == 5'b00000)
core/decoder.sv:875:-                    instruction_o.op = ariane_pkg::ZEXTH;
core/decoder.sv:876:-                  else
core/decoder.sv:877:-                    illegal_instr_bm = 1'b1;
core/decoder.sv:872:+                {
core/decoder.sv:873:+                  7'b000_0100, 3'b100
core/decoder.sv:874:+                } : begin
core/decoder.sv:875:+                  if (instr.instr[24:20] == 5'b00000) instruction_o.op = ariane_pkg::ZEXTH;
core/decoder.sv:876:+                  else illegal_instr_bm = 1'b1;
begin
Expand Down
2 changes: 1 addition & 1 deletion core/include/cv32a60x_config_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@ package cva6_config_pkg;
XF8: bit'(0),
RVA: bit'(0),
RVB: bit'(1),
ZKN: bit'(1),
ZKN: bit'(0),
RVV: bit'(0),
RVC: bit'(1),
RVH: bit'(0),
Expand Down
2 changes: 1 addition & 1 deletion core/include/cv32a65x_config_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@ package cva6_config_pkg;
XF8: bit'(0),
RVA: bit'(0),
RVB: bit'(1),
ZKN: bit'(1),
ZKN: bit'(0),
RVV: bit'(0),
RVC: bit'(1),
RVH: bit'(0),
Expand Down
3 changes: 1 addition & 2 deletions core/include/cv32a6_embedded_config_pkg_deprecated.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,6 @@ package cva6_config_pkg;
localparam CVA6ConfigAExtEn = 0;
localparam CVA6ConfigHExtEn = 0; // always disabled
localparam CVA6ConfigBExtEn = 1;
localparam CVA6ConfigZknExtEn = 0;
localparam CVA6ConfigVExtEn = 0;
localparam CVA6ConfigRVZiCond = 0;

Expand Down Expand Up @@ -91,7 +90,7 @@ package cva6_config_pkg;
XF8: bit'(CVA6ConfigF8En),
RVA: bit'(CVA6ConfigAExtEn),
RVB: bit'(CVA6ConfigBExtEn),
ZKN: bit'(CVA6ConfigZknExtEn),
ZKN: bit'(0),
RVV: bit'(CVA6ConfigVExtEn),
RVC: bit'(CVA6ConfigCExtEn),
RVH: bit'(CVA6ConfigHExtEn),
Expand Down
3 changes: 1 addition & 2 deletions core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,6 @@ package cva6_config_pkg;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigHExtEn = 0; // always disabled
localparam CVA6ConfigBExtEn = 0;
localparam CVA6ConfigZknExtEn = 0;
localparam CVA6ConfigVExtEn = 0;
localparam CVA6ConfigRVZiCond = 0;

Expand Down Expand Up @@ -92,7 +91,7 @@ package cva6_config_pkg;
XF8: bit'(CVA6ConfigF8En),
RVA: bit'(CVA6ConfigAExtEn),
RVB: bit'(CVA6ConfigBExtEn),
ZKN: bit'(CVA6ConfigZknExtEn),
ZKN: bit'(1),
RVV: bit'(CVA6ConfigVExtEn),
RVC: bit'(CVA6ConfigCExtEn),
RVH: bit'(CVA6ConfigHExtEn),
Expand Down
3 changes: 1 addition & 2 deletions core/include/cv32a6_imac_sv0_config_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,6 @@ package cva6_config_pkg;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigHExtEn = 0; // always disabled
localparam CVA6ConfigBExtEn = 0;
localparam CVA6ConfigZknExtEn = 0;
localparam CVA6ConfigVExtEn = 0;
localparam CVA6ConfigRVZiCond = 0;

Expand Down Expand Up @@ -92,7 +91,7 @@ package cva6_config_pkg;
XF8: bit'(CVA6ConfigF8En),
RVA: bit'(CVA6ConfigAExtEn),
RVB: bit'(CVA6ConfigBExtEn),
ZKN: bit'(CVA6ConfigZknExtEn),
ZKN: bit'(0),
RVV: bit'(CVA6ConfigVExtEn),
RVC: bit'(CVA6ConfigCExtEn),
RVH: bit'(CVA6ConfigHExtEn),
Expand Down
3 changes: 1 addition & 2 deletions core/include/cv32a6_imac_sv32_config_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,6 @@ package cva6_config_pkg;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigHExtEn = 0; // always disabled
localparam CVA6ConfigBExtEn = 0;
localparam CVA6ConfigZknExtEn = 0;
localparam CVA6ConfigVExtEn = 0;
localparam CVA6ConfigRVZiCond = 0;

Expand Down Expand Up @@ -92,7 +91,7 @@ package cva6_config_pkg;
XF8: bit'(CVA6ConfigF8En),
RVA: bit'(CVA6ConfigAExtEn),
RVB: bit'(CVA6ConfigBExtEn),
ZKN: bit'(CVA6ConfigZknExtEn),
ZKN: bit'(0),
RVV: bit'(CVA6ConfigVExtEn),
RVC: bit'(CVA6ConfigCExtEn),
RVH: bit'(CVA6ConfigHExtEn),
Expand Down
3 changes: 1 addition & 2 deletions core/include/cv32a6_imafc_sv32_config_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,6 @@ package cva6_config_pkg;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigHExtEn = 0; // always disabled
localparam CVA6ConfigBExtEn = 0;
localparam CVA6ConfigZknExtEn = 0;
localparam CVA6ConfigVExtEn = 0;
localparam CVA6ConfigRVZiCond = 0;

Expand Down Expand Up @@ -92,7 +91,7 @@ package cva6_config_pkg;
XF8: bit'(CVA6ConfigF8En),
RVA: bit'(CVA6ConfigAExtEn),
RVB: bit'(CVA6ConfigBExtEn),
ZKN: bit'(CVA6ConfigZknExtEn),
ZKN: bit'(0),
RVV: bit'(CVA6ConfigVExtEn),
RVC: bit'(CVA6ConfigCExtEn),
RVH: bit'(CVA6ConfigHExtEn),
Expand Down
3 changes: 1 addition & 2 deletions core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,6 @@ package cva6_config_pkg;
localparam CVA6ConfigZcmpExtEn = 0;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigBExtEn = 0;
localparam CVA6ConfigZknExtEn = 0;
localparam CVA6ConfigHExtEn = 0;
localparam CVA6ConfigVExtEn = 1;
localparam CVA6ConfigRVZiCond = 0;
Expand Down Expand Up @@ -92,7 +91,7 @@ package cva6_config_pkg;
XF8: bit'(CVA6ConfigF8En),
RVA: bit'(CVA6ConfigAExtEn),
RVB: bit'(CVA6ConfigBExtEn),
ZKN: bit'(CVA6ConfigZknExtEn),
ZKN: bit'(0),
RVV: bit'(CVA6ConfigVExtEn),
RVC: bit'(CVA6ConfigCExtEn),
RVH: bit'(CVA6ConfigHExtEn),
Expand Down
3 changes: 1 addition & 2 deletions core/include/cv64a6_imafdc_sv39_config_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,6 @@ package cva6_config_pkg;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigHExtEn = 0; // always disabled
localparam CVA6ConfigBExtEn = 1;
localparam CVA6ConfigZknExtEn = 1;
localparam CVA6ConfigVExtEn = 0;
localparam CVA6ConfigRVZiCond = 1;

Expand Down Expand Up @@ -92,7 +91,7 @@ package cva6_config_pkg;
XF8: bit'(CVA6ConfigF8En),
RVA: bit'(CVA6ConfigAExtEn),
RVB: bit'(CVA6ConfigBExtEn),
ZKN: bit'(CVA6ConfigZknExtEn),
ZKN: bit'(1),
RVV: bit'(CVA6ConfigVExtEn),
RVC: bit'(CVA6ConfigCExtEn),
RVH: bit'(CVA6ConfigHExtEn),
Expand Down
3 changes: 1 addition & 2 deletions core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,6 @@ package cva6_config_pkg;
localparam CVA6ConfigZcmpExtEn = 0;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigBExtEn = 1;
localparam CVA6ConfigZknExtEn = 1;
localparam CVA6ConfigVExtEn = 0;
localparam CVA6ConfigHExtEn = 0;
localparam CVA6ConfigRVZiCond = 1;
Expand Down Expand Up @@ -99,7 +98,7 @@ package cva6_config_pkg;
XF8: bit'(CVA6ConfigF8En),
RVA: bit'(CVA6ConfigAExtEn),
RVB: bit'(CVA6ConfigBExtEn),
ZKN: bit'(CVA6ConfigZknExtEn),
ZKN: bit'(1),
RVV: bit'(CVA6ConfigVExtEn),
RVC: bit'(CVA6ConfigCExtEn),
RVH: bit'(CVA6ConfigHExtEn),
Expand Down
3 changes: 1 addition & 2 deletions core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,6 @@ package cva6_config_pkg;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigHExtEn = 0; // always disabled
localparam CVA6ConfigBExtEn = 0;
localparam CVA6ConfigZknExtEn = 0;
localparam CVA6ConfigVExtEn = 0;
localparam CVA6ConfigRVZiCond = 0;

Expand Down Expand Up @@ -92,7 +91,7 @@ package cva6_config_pkg;
XF8: bit'(CVA6ConfigF8En),
RVA: bit'(CVA6ConfigAExtEn),
RVB: bit'(CVA6ConfigBExtEn),
ZKN: bit'(CVA6ConfigZknExtEn),
ZKN: bit'(0),
RVV: bit'(CVA6ConfigVExtEn),
RVC: bit'(CVA6ConfigCExtEn),
RVH: bit'(CVA6ConfigHExtEn),
Expand Down
Loading

0 comments on commit ae24f11

Please sign in to comment.