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conditioned RTL with XLEN parameter (#1579)
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@fatimasaleem
fatimasaleem authored Oct 31, 2023
1 parent 1faaec0 commit a99f115
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75 changes: 46 additions & 29 deletions core/alu.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -76,16 +76,21 @@ module alu
operand_a_bitmanip = fu_data_i.operand_a;

if (ariane_pkg::BITMANIP) begin
if (riscv::IS_XLEN64) begin
unique case (fu_data_i.operation)
SH1ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 1;
SH2ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 2;
SH3ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 3;
CTZW: operand_a_bitmanip = operand_a_rev32;
ADDUW, CPOPW, CLZW: operand_a_bitmanip = fu_data_i.operand_a[31:0];
default: ;
endcase
end
unique case (fu_data_i.operation)
SH1ADD: operand_a_bitmanip = fu_data_i.operand_a << 1;
SH2ADD: operand_a_bitmanip = fu_data_i.operand_a << 2;
SH3ADD: operand_a_bitmanip = fu_data_i.operand_a << 3;
SH1ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 1;
SH2ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 2;
SH3ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 3;
CTZ: operand_a_bitmanip = operand_a_rev;
CTZW: operand_a_bitmanip = operand_a_rev32;
ADDUW, CPOPW, CLZW: operand_a_bitmanip = fu_data_i.operand_a[31:0];
default: ;
endcase
end
Expand Down Expand Up @@ -209,21 +214,23 @@ module alu
.cnt_o(lz_tz_count),
.empty_o(lz_tz_empty)
);
//32b
lzc #(
.WIDTH(32),
.MODE (1)
) i_clz_32b (
.in_i(operand_a_bitmanip[31:0]),
.cnt_o(lz_tz_wcount),
.empty_o(lz_tz_wempty)
);
if (riscv::IS_XLEN64) begin
//32b
lzc #(
.WIDTH(32),
.MODE (1)
) i_clz_32b (
.in_i(operand_a_bitmanip[31:0]),
.cnt_o(lz_tz_wcount),
.empty_o(lz_tz_wempty)
);
end
end

if (ariane_pkg::BITMANIP) begin : gen_orcbw_rev8w_results
assign orcbw = {{8{|fu_data_i.operand_a[31:24]}}, {8{|fu_data_i.operand_a[23:16]}}, {8{|fu_data_i.operand_a[15:8]}}, {8{|fu_data_i.operand_a[7:0]}}};
assign rev8w = {{fu_data_i.operand_a[7:0]}, {fu_data_i.operand_a[15:8]}, {fu_data_i.operand_a[23:16]}, {fu_data_i.operand_a[31:24]}};
if (riscv::XLEN == 64) begin : gen_64b
if (riscv::IS_XLEN64) begin : gen_64b
assign orcbw_result = {{8{|fu_data_i.operand_a[63:56]}}, {8{|fu_data_i.operand_a[55:48]}}, {8{|fu_data_i.operand_a[47:40]}}, {8{|fu_data_i.operand_a[39:32]}}, orcbw};
assign rev8w_result = {rev8w , {fu_data_i.operand_a[39:32]}, {fu_data_i.operand_a[47:40]}, {fu_data_i.operand_a[55:48]}, {fu_data_i.operand_a[63:56]}};
end else begin : gen_32b
Expand All @@ -237,25 +244,28 @@ module alu
// -----------
always_comb begin
result_o = '0;
if (riscv::IS_XLEN64) begin
unique case (fu_data_i.operation)
// Add word: Ignore the upper bits and sign extend to 64 bit
ADDW, SUBW: result_o = {{riscv::XLEN - 32{adder_result[31]}}, adder_result[31:0]};
SH1ADDUW, SH2ADDUW, SH3ADDUW: result_o = adder_result;
// Shifts 32 bit
SLLW, SRLW, SRAW: result_o = {{riscv::XLEN - 32{shift_result32[31]}}, shift_result32[31:0]};
default: ;
endcase
end
unique case (fu_data_i.operation)
// Standard Operations
ANDL, ANDN: result_o = fu_data_i.operand_a & operand_b_neg[riscv::XLEN:1];
ORL, ORN: result_o = fu_data_i.operand_a | operand_b_neg[riscv::XLEN:1];
XORL, XNOR: result_o = fu_data_i.operand_a ^ operand_b_neg[riscv::XLEN:1];

// Adder Operations
ADD, SUB, ADDUW, SH1ADD, SH2ADD, SH3ADD, SH1ADDUW, SH2ADDUW, SH3ADDUW:
ADD, SUB, ADDUW, SH1ADD, SH2ADD, SH3ADD:
result_o = adder_result;
// Add word: Ignore the upper bits and sign extend to 64 bit
ADDW, SUBW: result_o = {{riscv::XLEN - 32{adder_result[31]}}, adder_result[31:0]};
// Shift Operations
SLL, SRL, SRA: result_o = (riscv::XLEN == 64) ? shift_result : shift_result32;
// Shifts 32 bit
SLLW, SRLW, SRAW: result_o = {{riscv::XLEN - 32{shift_result32[31]}}, shift_result32[31:0]};

SLL, SRL, SRA: result_o = (riscv::IS_XLEN64) ? shift_result : shift_result32;
// Comparison Operations
SLTS, SLTU: result_o = {{riscv::XLEN - 1{1'b0}}, less};

default: ; // default case to suppress unique warning
endcase

Expand All @@ -265,6 +275,14 @@ module alu
// rolw, roriw, rorw
rolw = ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[4:0]) | ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> (riscv::XLEN-32-fu_data_i.operand_b[4:0]));
rorw = ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> fu_data_i.operand_b[4:0]) | ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << (riscv::XLEN-32-fu_data_i.operand_b[4:0]));
if (riscv::IS_XLEN64) begin
unique case (fu_data_i.operation)
CLZW, CTZW: result_o = (lz_tz_wempty) ? 32 : {{riscv::XLEN - 5{1'b0}}, lz_tz_wcount}; // change
ROLW: result_o = {{riscv::XLEN - 32{rolw[31]}}, rolw};
RORW, RORIW: result_o = {{riscv::XLEN - 32{rorw[31]}}, rorw};
default: ;
endcase
end
unique case (fu_data_i.operation)
// Left Shift 32 bit unsigned
SLLIUW:
Expand All @@ -285,7 +303,6 @@ module alu
CLZ, CTZ:
result_o = (lz_tz_empty) ? ({{riscv::XLEN - $clog2(riscv::XLEN) {1'b0}}, lz_tz_count} + 1) :
{{riscv::XLEN - $clog2(riscv::XLEN) {1'b0}}, lz_tz_count};
CLZW, CTZW: result_o = (lz_tz_wempty) ? 32 : {{riscv::XLEN - 5{1'b0}}, lz_tz_wcount};

// Count population
CPOP, CPOPW: result_o = {{(riscv::XLEN - ($clog2(riscv::XLEN) + 1)) {1'b0}}, cpop};
Expand All @@ -297,11 +314,11 @@ module alu

// Bitwise Rotation
ROL:
result_o = (riscv::XLEN == 64) ? ((fu_data_i.operand_a << fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a >> (riscv::XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a << fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a >> (riscv::XLEN-fu_data_i.operand_b[4:0])));
ROLW: result_o = {{riscv::XLEN - 32{rolw[31]}}, rolw};
result_o = (riscv::IS_XLEN64) ? ((fu_data_i.operand_a << fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a >> (riscv::XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a << fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a >> (riscv::XLEN-fu_data_i.operand_b[4:0])));

ROR, RORI:
result_o = (riscv::XLEN == 64) ? ((fu_data_i.operand_a >> fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a << (riscv::XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a >> fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a << (riscv::XLEN-fu_data_i.operand_b[4:0])));
RORW, RORIW: result_o = {{riscv::XLEN - 32{rorw[31]}}, rorw};
result_o = (riscv::IS_XLEN64) ? ((fu_data_i.operand_a >> fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a << (riscv::XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a >> fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a << (riscv::XLEN-fu_data_i.operand_b[4:0])));

ORCB:
result_o = orcbw_result;
REV8:
Expand Down
81 changes: 45 additions & 36 deletions core/compressed_decoder.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -100,7 +100,7 @@ module compressed_decoder #(
// c.ld -> ld rd', imm(rs1')
// RV32
// c.flw -> flw fprd', imm(rs1')
if (riscv::XLEN == 64) begin
if (riscv::IS_XLEN64) begin
// CLD: | funct3 | imm[5:3] | rs1' | imm[7:6] | rd' | C0 |
instr_o = {
4'b0,
Expand Down Expand Up @@ -136,7 +136,7 @@ module compressed_decoder #(
if (CVA6Cfg.RVZCB) begin
unique case (instr_i[12:10])
3'b000: begin
// c.lbu -> lbu rd', uimm(rs1')
// c.lbu -> lbu rd', uimm(rs1')
instr_o = {
10'b0,
instr_i[5],
Expand All @@ -152,7 +152,7 @@ module compressed_decoder #(

3'b001: begin
if (instr_i[6]) begin
// c.lh -> lh rd', uimm(rs1')
// c.lh -> lh rd', uimm(rs1')
instr_o = {
10'b0,
instr_i[5],
Expand Down Expand Up @@ -181,7 +181,7 @@ module compressed_decoder #(
end

3'b010: begin
// c.sb -> sb rs2', uimm(rs1')
// c.sb -> sb rs2', uimm(rs1')
instr_o = {
7'b0,
2'b01,
Expand Down Expand Up @@ -263,7 +263,7 @@ module compressed_decoder #(
// c.sd -> sd rs2', imm(rs1')
// RV32
// c.fsw -> fsw fprs2', imm(rs1')
if (riscv::XLEN == 64) begin
if (riscv::IS_XLEN64) begin
instr_o = {
4'b0,
instr_i[6:5],
Expand Down Expand Up @@ -320,7 +320,7 @@ module compressed_decoder #(


riscv::OpcodeC1Addiw: begin // or riscv::OpcodeC1Jal for RV32IC
if (riscv::XLEN == 64) begin
if (riscv::IS_XLEN64) begin
// c.addiw -> addiw rd, rd, nzimm for RV64IC
if (instr_i[11:7] != 5'h0) begin // only valid if the destination is not r0
instr_o = {
Expand Down Expand Up @@ -493,34 +493,43 @@ module compressed_decoder #(
end

3'b100: begin
// c.subw -> subw rd', rd', rs2'
instr_o = {
2'b01,
5'b0,
2'b01,
instr_i[4:2],
2'b01,
instr_i[9:7],
3'b000,
2'b01,
instr_i[9:7],
riscv::OpcodeOp32
};
if (riscv::IS_XLEN64) begin
// c.subw -> subw rd', rd', rs2'
instr_o = {
2'b01,
5'b0,
2'b01,
instr_i[4:2],
2'b01,
instr_i[9:7],
3'b000,
2'b01,
instr_i[9:7],
riscv::OpcodeOp32
};
end else begin
illegal_instr_o = 1'b1;
end
end

3'b101: begin
// c.addw -> addw rd', rd', rs2'
instr_o = {
2'b00,
5'b0,
2'b01,
instr_i[4:2],
2'b01,
instr_i[9:7],
3'b000,
2'b01,
instr_i[9:7],
riscv::OpcodeOp32
};
if (riscv::IS_XLEN64) begin
// c.addw -> addw rd', rd', rs2'
instr_o = {
2'b00,
5'b0,
2'b01,
instr_i[4:2],
2'b01,
instr_i[9:7],
3'b000,
2'b01,
instr_i[9:7],
riscv::OpcodeOp32
};
end else begin
illegal_instr_o = 1'b1;
end
end

3'b110: begin
Expand Down Expand Up @@ -581,7 +590,7 @@ module compressed_decoder #(
3'b010: begin
if (ariane_pkg::BITMANIP) begin
// c.zext.h -> zext.h rd', rd'
if (riscv::XLEN == 64) begin
if (riscv::IS_XLEN64) begin
instr_o = {
7'h4,
5'h0,
Expand Down Expand Up @@ -626,7 +635,7 @@ module compressed_decoder #(
3'b100: begin
if (ariane_pkg::BITMANIP) begin
// c.zext.w -> add.uw
if (riscv::XLEN == 64) begin
if (riscv::IS_XLEN64) begin
instr_o = {
7'h4,
5'h0,
Expand Down Expand Up @@ -759,7 +768,7 @@ module compressed_decoder #(
// c.ldsp -> ld rd, imm(x2)
// RV32
// c.flwsp -> flw fprd, imm(x2)
if (riscv::XLEN == 64) begin
if (riscv::IS_XLEN64) begin
instr_o = {
3'b0,
instr_i[4:2],
Expand Down Expand Up @@ -847,7 +856,7 @@ module compressed_decoder #(
// c.sdsp -> sd rs2, imm(x2)
// RV32
// c.fswsp -> fsw fprs2, imm(x2)
if (riscv::XLEN == 64) begin
if (riscv::IS_XLEN64) begin
instr_o = {
3'b0,
instr_i[9:7],
Expand Down
13 changes: 12 additions & 1 deletion core/decoder.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -50,6 +50,7 @@ module decoder
logic illegal_instr_bm;
logic illegal_instr_zic;
logic illegal_instr_non_bm;
logic illegal_instr_non_zexth;
// this instruction is an environment call (ecall), it is handled like an exception
logic ecall;
// this instruction is a software break-point
Expand Down Expand Up @@ -107,6 +108,7 @@ module decoder
illegal_instr_non_bm = 1'b0;
illegal_instr_bm = 1'b0;
illegal_instr_zic = 1'b0;
illegal_instr_non_zexth = 1'b0;
instruction_o.pc = pc_i;
instruction_o.trans_id = '0;
instruction_o.fu = NONE;
Expand Down Expand Up @@ -629,6 +631,15 @@ module decoder
instruction_o.rs1[4:0] = instr.rtype.rs1;
instruction_o.rs2[4:0] = instr.rtype.rs2;
instruction_o.rd[4:0] = instr.rtype.rd;
if (ariane_pkg::BITMANIP) begin
unique case ({
instr.rtype.funct7, instr.rtype.funct3
})
// Zero Extend Op
{7'b000_0100, 3'b100}: instruction_o.op = ariane_pkg::ZEXTH; // zext
default: illegal_instr_non_zexth = 1'b1;
endcase
end
if (riscv::IS_XLEN64) begin
unique case ({
instr.rtype.funct7, instr.rtype.funct3
Expand Down Expand Up @@ -667,7 +678,7 @@ module decoder
end else begin
illegal_instr = illegal_instr_non_bm;
end
end else illegal_instr = 1'b1;
end else illegal_instr = ~illegal_instr_non_zexth;
end
// --------------------------------
// Reg-Immediate Operations
Expand Down

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