removed c.zext.w from rv32 spec (#1563)

Signed-off-by: Abdul Wadood <[email protected]>
openhwgroup · Oct 23, 2023 · 9e47cc6 · 9e47cc6
1 parent 38b1da2
commit 9e47cc6
Showing 1 changed file with 0 additions and 12 deletions.
diff --git a/docs/01_cva6_user/RISCV_Instructions.rst b/docs/01_cva6_user/RISCV_Instructions.rst
@@ -1307,18 +1307,6 @@ All the Zcb instructions require at least standard C extension support as pre-re
 
     **Exception raised**: NONE
 
-- **C.ZEXT.W**: Compressed Zero Extend Word
-
-    **Format**: c.zext.w rd'
-
-    **Description**: This instruction takes a single source/destination operand. It zero-extends the least-significant word of the operand by inserting zeros into all of the bits more significant than 31. It also requires Bit-Manipulation (Zbb) extension support.
-
-    **Pseudocode**: x[8 + rd'] = zext(x[8 + rd'][31:0])
-
-    **Invalid values**: NONE
-
-    **Exception raised**: NONE
-
 - **C.NOT**: Compressed Bitwise NOT
 
     **Format**: c.not rd'